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Robotpkg Work In Progress

Generate ROM with attacks for Rehad-Orca.

For synthesis, place mem.hex in ip/idram/src/input. [Request GCC cross compiler (RV32IM).] For bitsteam, replace BRAM content of myorca.bit. [Request Xilinx ISE setup and liscence.]

Modification of RISC-V softcore processor Orca.

REHAD: Using Low-Frequency Reconfigurable Hardware for Cache Side-Channel Attacks Detection. Run on ML605 evaluation board with UART 115200.

Ethernet MAC 10/100Mbps IP (OpenCores) with AXI4 (Lite) interface.

Has Linux driver support.

Try to adapt Mastik Toolkit to RISC-V

Cache side channel attacks for RISC-V (also works for x86)

Code source of the Monte-Carlo Tree search, published at CP2021

3D model of the Gerard Bauzil experimental room.

A generator of Return-Oriented Programming on RISC-V

This is the official Low Side Synchronous Buck converter Gitlab

Build benchmark for RISC-V (default to RV64IMAC)

Bootloader (@6000_0000) that receive file from UART and write to DDR (@8000_0000)

Linux Module for : 1) R/W mmio registers. 2) Context change send info. 3) Interrupts handler.

Boot a 32-bit/64-bit RISC-V Linux!

With support for Matana kernel module.

For 32-bit target, the simulation with Spike or QEMU is broken, but works on real hardware. The Ethernet (opencores) support is for 32-bit only.