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Livre d'introduction à ROS

Modification of RISC-V softcore processor Orca.

REHAD: Using Low-Frequency Reconfigurable Hardware for Cache Side-Channel Attacks Detection. Run on ML605 evaluation board with UART 115200.

MATANA Implementation on Chipyard (Rocket-Chip RISC-V Softcore processor) on ML605 board

3D model of the Gerard Bauzil experimental room.

Sample and basic use of LaTeX beamer theme

Boot a 32-bit/64-bit RISC-V Linux!

With support for Matana kernel module.

For 32-bit target, the simulation with Spike or QEMU is broken, but works on real hardware. The Ethernet (opencores) support is for 32-bit only.

This package is intended to ease construction of CORBA servers by templating actions that are common to all servers.

Resource-Constrained Scheduling Solver based on difference logic and clause learning