Explore projects
-
Updated
-
Modification of RISC-V softcore processor Orca.
REHAD: Using Low-Frequency Reconfigurable Hardware for Cache Side-Channel Attacks Detection. Run on ML605 evaluation board with UART 115200.
Updated -
MATANA Implementation on Chipyard (Rocket-Chip RISC-V Softcore processor) on ML605 board
Updated -
-
Updated
-
-
Updated
-
Document de travail pour les cours de ROS-2 à l'ANF en septembre 2022
Updated -
Code source of the Monte-Carlo Tree search, published at CP2021
Updated -
Updated
-
Updated
-
Updated
-
Customized rddlsim version for my personal use
Updated -
-
Updated
-
-
-
network diagnostic tool using the UDP echo service (not ICMP echo because some vendors cheat and prioritize ICMP echo packets to show healthy connections)
Updated -
Generate ROM with attacks for Rehad-Orca.
For synthesis, place mem.hex in ip/idram/src/input. [Request GCC cross compiler (RV32IM).] For bitsteam, replace BRAM content of myorca.bit. [Request Xilinx ISE setup and liscence.]Updated -
Updated