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Modification of RISC-V softcore processor Orca.

REHAD: Using Low-Frequency Reconfigurable Hardware for Cache Side-Channel Attacks Detection. Run on ML605 evaluation board with UART 115200.

MATANA Implementation on Chipyard (Rocket-Chip RISC-V Softcore processor) on ML605 board

Livre d'introduction à ROS

Robotpkg Work In Progress

Fork from https://git.openrobots.org/robots/robotpkg.git

Document de travail pour les cours de ROS-2 à l'ANF en septembre 2022

Code source of the Monte-Carlo Tree search, published at CP2021

Customized rddlsim version for my personal use

BE INSA

Build benchmark for RISC-V (default to RV64IMAC)

Tor based on ABE

network diagnostic tool using the UDP echo service (not ICMP echo because some vendors cheat and prioritize ICMP echo packets to show healthy connections)

Generate ROM with attacks for Rehad-Orca.

For synthesis, place mem.hex in ip/idram/src/input. [Request GCC cross compiler (RV32IM).] For bitsteam, replace BRAM content of myorca.bit. [Request Xilinx ISE setup and liscence.]