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Clone of https://git.openrobots.org/projects/robotpkg with branches prepared for the CI of other projects

Fork from https://git.openrobots.org/robots/robotpkg.git

Generate ROM with attacks for Rehad-Orca.

For synthesis, place mem.hex in ip/idram/src/input. [Request GCC cross compiler (RV32IM).] For bitsteam, replace BRAM content of myorca.bit. [Request Xilinx ISE setup and liscence.]

Modification of RISC-V softcore processor Orca.

REHAD: Using Low-Frequency Reconfigurable Hardware for Cache Side-Channel Attacks Detection. Run on ML605 evaluation board with UART 115200.

Customized rddlsim version for my personal use

Code source of the Monte-Carlo Tree search, published at CP2021

MATANA Implementation on Chipyard (Rocket-Chip RISC-V Softcore processor) on ML605 board

Linux Module for : 1) R/W mmio registers. 2) Context change send info. 3) Interrupts handler.

Try to adapt Mastik Toolkit to RISC-V

This is the official Low Side Synchronous Buck converter Gitlab

Boot a 32-bit/64-bit RISC-V Linux!

With support for Matana kernel module.

For 32-bit target, the simulation with Spike or QEMU is broken, but works on real hardware. The Ethernet (opencores) support is for 32-bit only.