Explore projects

Modification of RISC-V softcore processor Orca.

REHAD: Using Low-Frequency Reconfigurable Hardware for Cache Side-Channel Attacks Detection. Run on ML605 evaluation board with UART 115200.

MATANA Implementation on Chipyard (Rocket-Chip RISC-V Softcore processor) on ML605 board

Livre d'introduction à ROS

Boot a 32-bit/64-bit RISC-V Linux!

With support for Matana kernel module.

For 32-bit target, the simulation with Spike or QEMU is broken, but works on real hardware. The Ethernet (opencores) support is for 32-bit only.

3D model of the Gerard Bauzil experimental room.

A generator of Return-Oriented Programming on RISC-V

Bootloader (@6000_0000) that receive file from UART and write to DDR (@8000_0000)

Modèle de thèse initialement publié à git:redmine du LAAS. Télécharger et utiliser en locale (besoin latexmk + pdflatex je crois), ou en Overleaf. N'hésite pas à l'améliorer!

Ethernet MAC 10/100Mbps IP (OpenCores) with AXI4 (Lite) interface.

Has Linux driver support.