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Livre d'introduction à ROS

Modification of RISC-V softcore processor Orca.

REHAD: Using Low-Frequency Reconfigurable Hardware for Cache Side-Channel Attacks Detection. Run on ML605 evaluation board with UART 115200.

MATANA Implementation on Chipyard (Rocket-Chip RISC-V Softcore processor) on ML605 board

Sample and basic use of LaTeX beamer theme

3D model of the Gerard Bauzil experimental room.

This package is intended to ease construction of CORBA servers by templating actions that are common to all servers.

Cache side channel attacks for RISC-V (also works for x86)

Priority allocation algorithms for the oMDP

This is the official Low Side Synchronous Buck converter Gitlab