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Modification of RISC-V softcore processor Orca.

REHAD: Using Low-Frequency Reconfigurable Hardware for Cache Side-Channel Attacks Detection. Run on ML605 evaluation board with UART 115200.

MATANA Implementation on Chipyard (Rocket-Chip RISC-V Softcore processor) on ML605 board

Livre d'introduction à ROS

Generate ROM with attacks for Rehad-Orca.

For synthesis, place mem.hex in ip/idram/src/input. [Request GCC cross compiler (RV32IM).] For bitsteam, replace BRAM content of myorca.bit. [Request Xilinx ISE setup and liscence.]

BE INSA

3D model of the Gerard Bauzil experimental room.

Build benchmark for RISC-V (default to RV64IMAC)

Tor based on ABE