.gitignore

@@ -5,9 +5,6 @@ TP_MLP.gen/
 TP_MLP.cache/
 TP_MLP.sim/
 data/
-*.xpr
-*.wcfg
-*.pt
 mnist_mlp/data_files/
 mnist_mlp/bin/
 mnist_mlp/__pycache__/

vivado.jou

@@ -3,8 +3,8 @@
 # SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
 # IP Build 5075265 on Wed May 22 21:45:21 MDT 2024
 # SharedData Build 5076995 on Wed May 22 18:29:18 MDT 2024
-# Start of session at: Tue Dec 31 14:31:47 2024
-# Process ID: 54225
+# Start of session at: Tue Dec 31 14:36:31 2024
+# Process ID: 55168
 # Current directory: /home/achoul/AI_ON_FPGA/TP_MLP
 # Command line: vivado
 # Log file: /home/achoul/AI_ON_FPGA/TP_MLP/vivado.log
@@ -13,14 +13,31 @@
 # Platform          :Linuxmint
 # Operating System  :Linux Mint 21.3
 # Processor Detail  :Intel(R) Core(TM) i7-6700HQ CPU @ 2.60GHz
-# CPU Frequency     :2600.000 MHz
+# CPU Frequency     :3257.715 MHz
 # CPU Physical cores:4
 # CPU Logical cores :8
 # Host memory       :16619 MB
 # Swap memory       :1027 MB
 # Total Virtual     :17647 MB
-# Available Virtual :9328 MB
+# Available Virtual :9372 MB
 #-----------------------------------------------------------
 start_gui
 open_project /home/achoul/AI_ON_FPGA/TP_MLP/TP_MLP.xpr
 update_compile_order -fileset sources_1
+update_compile_order -fileset sim_1
+export_ip_user_files -of_objects  [get_files /home/achoul/AI_ON_FPGA/TP_MLP/TP_MLP.srcs/sources_1/new/HardTanh.vhd] -no_script -reset -force -quiet
+export_ip_user_files -of_objects  [get_files /home/achoul/AI_ON_FPGA/TP_MLP/TP_MLP.srcs/sources_1/new/Interface.vhd] -no_script -reset -force -quiet
+export_ip_user_files -of_objects  [get_files /home/achoul/AI_ON_FPGA/TP_MLP/TP_MLP.srcs/sources_1/new/ReLU.vhd] -no_script -reset -force -quiet
+export_ip_user_files -of_objects  [get_files /home/achoul/AI_ON_FPGA/TP_MLP/TP_MLP.srcs/sources_1/new/function_pkg.vhd] -no_script -reset -force -quiet
+export_ip_user_files -of_objects  [get_files /home/achoul/AI_ON_FPGA/TP_MLP/TP_MLP.srcs/sources_1/new/hardmax.vhd] -no_script -reset -force -quiet
+export_ip_user_files -of_objects  [get_files /home/achoul/AI_ON_FPGA/TP_MLP/TP_MLP.srcs/sources_1/new/layer.vhd] -no_script -reset -force -quiet
+export_ip_user_files -of_objects  [get_files /home/achoul/AI_ON_FPGA/TP_MLP/TP_MLP.srcs/sources_1/new/network.vhd] -no_script -reset -force -quiet
+export_ip_user_files -of_objects  [get_files /home/achoul/AI_ON_FPGA/TP_MLP/TP_MLP.srcs/sources_1/new/perceptron.vhd] -no_script -reset -force -quiet
+remove_files  {/home/achoul/AI_ON_FPGA/TP_MLP/TP_MLP.srcs/sources_1/new/HardTanh.vhd /home/achoul/AI_ON_FPGA/TP_MLP/TP_MLP.srcs/sources_1/new/Interface.vhd /home/achoul/AI_ON_FPGA/TP_MLP/TP_MLP.srcs/sources_1/new/ReLU.vhd /home/achoul/AI_ON_FPGA/TP_MLP/TP_MLP.srcs/sources_1/new/function_pkg.vhd /home/achoul/AI_ON_FPGA/TP_MLP/TP_MLP.srcs/sources_1/new/hardmax.vhd /home/achoul/AI_ON_FPGA/TP_MLP/TP_MLP.srcs/sources_1/new/layer.vhd /home/achoul/AI_ON_FPGA/TP_MLP/TP_MLP.srcs/sources_1/new/network.vhd /home/achoul/AI_ON_FPGA/TP_MLP/TP_MLP.srcs/sources_1/new/perceptron.vhd}
+export_ip_user_files -of_objects  [get_files /home/achoul/AI_ON_FPGA/TP_MLP/TP_MLP.srcs/sim_1/new/tb_layer.vhd] -no_script -reset -force -quiet
+export_ip_user_files -of_objects  [get_files /home/achoul/AI_ON_FPGA/TP_MLP/TP_MLP.srcs/sim_1/new/tb_network.vhd] -no_script -reset -force -quiet
+export_ip_user_files -of_objects  [get_files /home/achoul/AI_ON_FPGA/TP_MLP/TP_MLP.srcs/sim_1/new/tb_perceptron.vhd] -no_script -reset -force -quiet
+export_ip_user_files -of_objects  [get_files /home/achoul/AI_ON_FPGA/TP_MLP/TP_MLP.srcs/sim_1/new/test_fixe_point.vhd] -no_script -reset -force -quiet
+export_ip_user_files -of_objects  [get_files /home/achoul/AI_ON_FPGA/TP_MLP/TP_MLP.srcs/sim_1/new/test_text_io.vhd] -no_script -reset -force -quiet
+export_ip_user_files -of_objects  [get_files /home/achoul/AI_ON_FPGA/TP_MLP/TP_MLP.srcs/sim_1/new/whole_system_tb.vhd] -no_script -reset -force -quiet
+remove_files  -fileset sim_1 {/home/achoul/AI_ON_FPGA/TP_MLP/TP_MLP.srcs/sim_1/new/tb_layer.vhd /home/achoul/AI_ON_FPGA/TP_MLP/TP_MLP.srcs/sim_1/new/tb_network.vhd /home/achoul/AI_ON_FPGA/TP_MLP/TP_MLP.srcs/sim_1/new/tb_perceptron.vhd /home/achoul/AI_ON_FPGA/TP_MLP/TP_MLP.srcs/sim_1/new/test_fixe_point.vhd /home/achoul/AI_ON_FPGA/TP_MLP/TP_MLP.srcs/sim_1/new/test_text_io.vhd /home/achoul/AI_ON_FPGA/TP_MLP/TP_MLP.srcs/sim_1/new/whole_system_tb.vhd}

vivado.log

@@ -3,8 +3,8 @@
 # SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
 # IP Build 5075265 on Wed May 22 21:45:21 MDT 2024
 # SharedData Build 5076995 on Wed May 22 18:29:18 MDT 2024
-# Start of session at: Tue Dec 31 14:31:47 2024
-# Process ID: 54225
+# Start of session at: Tue Dec 31 14:36:31 2024
+# Process ID: 55168
 # Current directory: /home/achoul/AI_ON_FPGA/TP_MLP
 # Command line: vivado
 # Log file: /home/achoul/AI_ON_FPGA/TP_MLP/vivado.log
@@ -13,13 +13,13 @@
 # Platform          :Linuxmint
 # Operating System  :Linux Mint 21.3
 # Processor Detail  :Intel(R) Core(TM) i7-6700HQ CPU @ 2.60GHz
-# CPU Frequency     :2600.000 MHz
+# CPU Frequency     :3257.715 MHz
 # CPU Physical cores:4
 # CPU Logical cores :8
 # Host memory       :16619 MB
 # Swap memory       :1027 MB
 # Total Virtual     :17647 MB
-# Available Virtual :9328 MB
+# Available Virtual :9372 MB
 #-----------------------------------------------------------
 start_gui
 open_project /home/achoul/AI_ON_FPGA/TP_MLP/TP_MLP.xpr
@@ -84,12 +84,43 @@ WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216:part0:2.0 availab
 WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld:part0:2.0 available at /tools/Xilinx/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/production/2.0/board.xml as part xczu59dr-ffvf1760-2-i specified in board_part file is either invalid or not available
 WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670:part0:2.0 available at /tools/Xilinx/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670/2.0/board.xml as part xczu67dr-fsve1156-2-i specified in board_part file is either invalid or not available
 WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670ld:part0:1.0 available at /tools/Xilinx/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670ld/1.0/board.xml as part xczu57dr-fsve1156-2-i specified in board_part file is either invalid or not available
+CRITICAL WARNING: [Project 1-19] Could not find the file '/home/achoul/AI_ON_FPGA/TP_MLP/TP_MLP.srcs/sources_1/new/function_pkg.vhd'.
+CRITICAL WARNING: [Project 1-19] Could not find the file '/home/achoul/AI_ON_FPGA/TP_MLP/TP_MLP.srcs/sources_1/new/HardTanh.vhd'.
+CRITICAL WARNING: [Project 1-19] Could not find the file '/home/achoul/AI_ON_FPGA/TP_MLP/TP_MLP.srcs/sources_1/new/ReLU.vhd'.
+CRITICAL WARNING: [Project 1-19] Could not find the file '/home/achoul/AI_ON_FPGA/TP_MLP/TP_MLP.srcs/sources_1/new/hardmax.vhd'.
+CRITICAL WARNING: [Project 1-19] Could not find the file '/home/achoul/AI_ON_FPGA/TP_MLP/TP_MLP.srcs/sources_1/new/layer.vhd'.
+CRITICAL WARNING: [Project 1-19] Could not find the file '/home/achoul/AI_ON_FPGA/TP_MLP/TP_MLP.srcs/sources_1/new/network.vhd'.
+CRITICAL WARNING: [Project 1-19] Could not find the file '/home/achoul/AI_ON_FPGA/TP_MLP/TP_MLP.srcs/sources_1/new/perceptron.vhd'.
+CRITICAL WARNING: [Project 1-19] Could not find the file '/home/achoul/AI_ON_FPGA/TP_MLP/TP_MLP.srcs/sources_1/new/Interface.vhd'.
+CRITICAL WARNING: [Project 1-19] Could not find the file '/home/achoul/AI_ON_FPGA/TP_MLP/TP_MLP.srcs/sim_1/new/tb_layer.vhd'.
+CRITICAL WARNING: [Project 1-19] Could not find the file '/home/achoul/AI_ON_FPGA/TP_MLP/TP_MLP.srcs/sim_1/new/tb_network.vhd'.
+CRITICAL WARNING: [Project 1-19] Could not find the file '/home/achoul/AI_ON_FPGA/TP_MLP/TP_MLP.srcs/sim_1/new/whole_system_tb.vhd'.
+CRITICAL WARNING: [Project 1-19] Could not find the file '/home/achoul/AI_ON_FPGA/TP_MLP/TP_MLP.srcs/sim_1/new/test_fixe_point.vhd'.
+CRITICAL WARNING: [Project 1-19] Could not find the file '/home/achoul/AI_ON_FPGA/TP_MLP/TP_MLP.srcs/sim_1/new/test_text_io.vhd'.
+CRITICAL WARNING: [Project 1-19] Could not find the file '/home/achoul/AI_ON_FPGA/TP_MLP/TP_MLP.srcs/sim_1/new/tb_perceptron.vhd'.
 Scanning sources...
 Finished scanning sources
 INFO: [IP_Flow 19-234] Refreshing IP repositories
 INFO: [IP_Flow 19-1704] No user IP repositories specified
 INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2024.1/data/ip'.
-open_project: Time (s): cpu = 00:00:24 ; elapsed = 00:00:12 . Memory (MB): peak = 8003.152 ; gain = 490.383 ; free physical = 2421 ; free virtual = 7809
+open_project: Time (s): cpu = 00:00:24 ; elapsed = 00:00:12 . Memory (MB): peak = 7983.617 ; gain = 478.625 ; free physical = 2460 ; free virtual = 7850
 update_compile_order -fileset sources_1
+update_compile_order -fileset sim_1
+export_ip_user_files -of_objects  [get_files /home/achoul/AI_ON_FPGA/TP_MLP/TP_MLP.srcs/sources_1/new/HardTanh.vhd] -no_script -reset -force -quiet
+export_ip_user_files -of_objects  [get_files /home/achoul/AI_ON_FPGA/TP_MLP/TP_MLP.srcs/sources_1/new/Interface.vhd] -no_script -reset -force -quiet
+export_ip_user_files -of_objects  [get_files /home/achoul/AI_ON_FPGA/TP_MLP/TP_MLP.srcs/sources_1/new/ReLU.vhd] -no_script -reset -force -quiet
+export_ip_user_files -of_objects  [get_files /home/achoul/AI_ON_FPGA/TP_MLP/TP_MLP.srcs/sources_1/new/function_pkg.vhd] -no_script -reset -force -quiet
+export_ip_user_files -of_objects  [get_files /home/achoul/AI_ON_FPGA/TP_MLP/TP_MLP.srcs/sources_1/new/hardmax.vhd] -no_script -reset -force -quiet
+export_ip_user_files -of_objects  [get_files /home/achoul/AI_ON_FPGA/TP_MLP/TP_MLP.srcs/sources_1/new/layer.vhd] -no_script -reset -force -quiet
+export_ip_user_files -of_objects  [get_files /home/achoul/AI_ON_FPGA/TP_MLP/TP_MLP.srcs/sources_1/new/network.vhd] -no_script -reset -force -quiet
+export_ip_user_files -of_objects  [get_files /home/achoul/AI_ON_FPGA/TP_MLP/TP_MLP.srcs/sources_1/new/perceptron.vhd] -no_script -reset -force -quiet
+remove_files  {/home/achoul/AI_ON_FPGA/TP_MLP/TP_MLP.srcs/sources_1/new/HardTanh.vhd /home/achoul/AI_ON_FPGA/TP_MLP/TP_MLP.srcs/sources_1/new/Interface.vhd /home/achoul/AI_ON_FPGA/TP_MLP/TP_MLP.srcs/sources_1/new/ReLU.vhd /home/achoul/AI_ON_FPGA/TP_MLP/TP_MLP.srcs/sources_1/new/function_pkg.vhd /home/achoul/AI_ON_FPGA/TP_MLP/TP_MLP.srcs/sources_1/new/hardmax.vhd /home/achoul/AI_ON_FPGA/TP_MLP/TP_MLP.srcs/sources_1/new/layer.vhd /home/achoul/AI_ON_FPGA/TP_MLP/TP_MLP.srcs/sources_1/new/network.vhd /home/achoul/AI_ON_FPGA/TP_MLP/TP_MLP.srcs/sources_1/new/perceptron.vhd}
+export_ip_user_files -of_objects  [get_files /home/achoul/AI_ON_FPGA/TP_MLP/TP_MLP.srcs/sim_1/new/tb_layer.vhd] -no_script -reset -force -quiet
+export_ip_user_files -of_objects  [get_files /home/achoul/AI_ON_FPGA/TP_MLP/TP_MLP.srcs/sim_1/new/tb_network.vhd] -no_script -reset -force -quiet
+export_ip_user_files -of_objects  [get_files /home/achoul/AI_ON_FPGA/TP_MLP/TP_MLP.srcs/sim_1/new/tb_perceptron.vhd] -no_script -reset -force -quiet
+export_ip_user_files -of_objects  [get_files /home/achoul/AI_ON_FPGA/TP_MLP/TP_MLP.srcs/sim_1/new/test_fixe_point.vhd] -no_script -reset -force -quiet
+export_ip_user_files -of_objects  [get_files /home/achoul/AI_ON_FPGA/TP_MLP/TP_MLP.srcs/sim_1/new/test_text_io.vhd] -no_script -reset -force -quiet
+export_ip_user_files -of_objects  [get_files /home/achoul/AI_ON_FPGA/TP_MLP/TP_MLP.srcs/sim_1/new/whole_system_tb.vhd] -no_script -reset -force -quiet
+remove_files  -fileset sim_1 {/home/achoul/AI_ON_FPGA/TP_MLP/TP_MLP.srcs/sim_1/new/tb_layer.vhd /home/achoul/AI_ON_FPGA/TP_MLP/TP_MLP.srcs/sim_1/new/tb_network.vhd /home/achoul/AI_ON_FPGA/TP_MLP/TP_MLP.srcs/sim_1/new/tb_perceptron.vhd /home/achoul/AI_ON_FPGA/TP_MLP/TP_MLP.srcs/sim_1/new/test_fixe_point.vhd /home/achoul/AI_ON_FPGA/TP_MLP/TP_MLP.srcs/sim_1/new/test_text_io.vhd /home/achoul/AI_ON_FPGA/TP_MLP/TP_MLP.srcs/sim_1/new/whole_system_tb.vhd}
 exit
-INFO: [Common 17-206] Exiting Vivado at Tue Dec 31 14:32:32 2024...
+INFO: [Common 17-206] Exiting Vivado at Tue Dec 31 14:37:46 2024...

vivado_54225.backup.jou

+#-----------------------------------------------------------
+# Vivado v2024.1 (64-bit)
+# SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
+# IP Build 5075265 on Wed May 22 21:45:21 MDT 2024
+# SharedData Build 5076995 on Wed May 22 18:29:18 MDT 2024
+# Start of session at: Tue Dec 31 14:31:47 2024
+# Process ID: 54225
+# Current directory: /home/achoul/AI_ON_FPGA/TP_MLP
+# Command line: vivado
+# Log file: /home/achoul/AI_ON_FPGA/TP_MLP/vivado.log
+# Journal file: /home/achoul/AI_ON_FPGA/TP_MLP/vivado.jou
+# Running On        :Gros-PC-PT
+# Platform          :Linuxmint
+# Operating System  :Linux Mint 21.3
+# Processor Detail  :Intel(R) Core(TM) i7-6700HQ CPU @ 2.60GHz
+# CPU Frequency     :2600.000 MHz
+# CPU Physical cores:4
+# CPU Logical cores :8
+# Host memory       :16619 MB
+# Swap memory       :1027 MB
+# Total Virtual     :17647 MB
+# Available Virtual :9328 MB
+#-----------------------------------------------------------
+start_gui
+open_project /home/achoul/AI_ON_FPGA/TP_MLP/TP_MLP.xpr
+update_compile_order -fileset sources_1

vivado_54225.backup.log

+#-----------------------------------------------------------
+# Vivado v2024.1 (64-bit)
+# SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
+# IP Build 5075265 on Wed May 22 21:45:21 MDT 2024
+# SharedData Build 5076995 on Wed May 22 18:29:18 MDT 2024
+# Start of session at: Tue Dec 31 14:31:47 2024
+# Process ID: 54225
+# Current directory: /home/achoul/AI_ON_FPGA/TP_MLP
+# Command line: vivado
+# Log file: /home/achoul/AI_ON_FPGA/TP_MLP/vivado.log
+# Journal file: /home/achoul/AI_ON_FPGA/TP_MLP/vivado.jou
+# Running On        :Gros-PC-PT
+# Platform          :Linuxmint
+# Operating System  :Linux Mint 21.3
+# Processor Detail  :Intel(R) Core(TM) i7-6700HQ CPU @ 2.60GHz
+# CPU Frequency     :2600.000 MHz
+# CPU Physical cores:4
+# CPU Logical cores :8
+# Host memory       :16619 MB
+# Swap memory       :1027 MB
+# Total Virtual     :17647 MB
+# Available Virtual :9328 MB
+#-----------------------------------------------------------
+start_gui
+open_project /home/achoul/AI_ON_FPGA/TP_MLP/TP_MLP.xpr
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:kc705:part0:1.6 available at /tools/Xilinx/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kc705/1.6/board.xml as part xc7k325tffg900-2 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu105:part0:1.6 available at /tools/Xilinx/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu105/1.6/board.xml as part xcku040-ffva1156-2-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu105:part0:1.7 available at /tools/Xilinx/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu105/1.7/board.xml as part xcku040-ffva1156-2-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu1500:part0:1.2 available at /tools/Xilinx/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu1500/1.2/board.xml as part xcku115-flvb2104-2-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vc707:part0:1.4 available at /tools/Xilinx/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vc707/1.4/board.xml as part xc7vx485tffg1761-2 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vc709:part0:1.8 available at /tools/Xilinx/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vc709/1.8/board.xml as part xc7vx690tffg1761-2 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190:part0:2.2 available at /tools/Xilinx/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vck190/production/2.2/board.xml as part xcvc1902-vsva2197-2mp-e-s specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190:part0:3.0 available at /tools/Xilinx/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vck190/production/3.0/board.xml as part xcvc1902-vsva2197-2mp-e-s specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190:part0:3.1 available at /tools/Xilinx/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vck190/production/3.1/board.xml as part xcvc1902-vsva2197-2mp-e-s specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190:part0:3.2 available at /tools/Xilinx/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vck190/production/3.2/board.xml as part xcvc1902-vsva2197-2mp-e-s specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190:part0:3.3 available at /tools/Xilinx/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vck190/production/3.3/board.xml as part xcvc1902-vsva2197-2mp-e-s specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190_newl:part0:1.0 available at /tools/Xilinx/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vck190_newl/production/1.0/board.xml as part xcvc1902-vsva2197-2mp-e-s specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190_newl:part0:1.1 available at /tools/Xilinx/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vck190_newl/production/1.1/board.xml as part xcvc1902-vsva2197-2mp-e-s specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190_newl:part0:1.2 available at /tools/Xilinx/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vck190_newl/production/1.2/board.xml as part xcvc1902-vsva2197-2mp-e-s specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu108:part0:1.6 available at /tools/Xilinx/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu108/1.6/board.xml as part xcvu095-ffva2104-2-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu108:part0:1.7 available at /tools/Xilinx/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu108/1.7/board.xml as part xcvu095-ffva2104-2-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu110:part0:1.4 available at /tools/Xilinx/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu110/1.4/board.xml as part xcvu190-flgc2104-2-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu118:part0:2.0 available at /tools/Xilinx/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu118/2.0/board.xml as part xcvu9p-flga2104-2l-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu118:part0:2.3 available at /tools/Xilinx/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu118/2.3/board.xml as part xcvu9p-flga2104-2l-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu118:part0:2.4 available at /tools/Xilinx/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu118/2.4/board.xml as part xcvu9p-flga2104-2l-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu129:part0:1.0 available at /tools/Xilinx/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu129/production/1.0/board.xml as part xcvu29p-fsga2577-2l-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu1525:part0:1.3 available at /tools/Xilinx/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu1525/1.3/board.xml as part xcvu9p-fsgd2104-2l-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280:part0:1.0 available at /tools/Xilinx/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/production/1.0/board.xml as part xcve2802-vsvh1760-2mp-e-s specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280:part0:1.1 available at /tools/Xilinx/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/production/1.1/board.xml as part xcve2802-vsvh1760-2mp-e-s specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280:part0:1.2 available at /tools/Xilinx/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/production/1.2/board.xml as part xcve2802-vsvh1760-2mp-e-s specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280_es:part0:1.0 available at /tools/Xilinx/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/es/rev_a/1.0/board.xml as part xcve2802-vsvh1760-2lp-e-s-es1 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280_es:part0:1.1 available at /tools/Xilinx/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/es/rev_a/1.1/board.xml as part xcve2802-vsvh1760-2lp-e-s-es1 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280_es_revb:part0:1.0 available at /tools/Xilinx/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/es/rev_b/1.0/board.xml as part xcve2802-vsvh1760-2mp-e-s-es1 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280_es_revb:part0:1.1 available at /tools/Xilinx/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/es/rev_b/1.1/board.xml as part xcve2802-vsvh1760-2mp-e-s-es1 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vermeo_t1_mpsoc:part0:1.0 available at /tools/Xilinx/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vermeo_t1_mpsoc/1.0/board.xml as part xczu19eg-ffvd1760-2l-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vermeo_t1_rfsoc:part0:1.0 available at /tools/Xilinx/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vermeo_t1_rfsoc/1.0/board.xml as part xczu21dr-ffvd1156-2l-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vhk158:part0:1.0 available at /tools/Xilinx/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vhk158/production/1.0/board.xml as part xcvh1582-vsva3697-2mp-e-s specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vhk158:part0:1.1 available at /tools/Xilinx/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vhk158/production/1.1/board.xml as part xcvh1582-vsva3697-2mp-e-s specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vhk158_es:part0:1.0 available at /tools/Xilinx/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vhk158/es/1.0/board.xml as part xcvh1582-vsva3697-2mp-e-s-es1 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vhk158_es:part0:1.1 available at /tools/Xilinx/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vhk158/es/1.1/board.xml as part xcvh1582-vsva3697-2mp-e-s-es1 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180:part0:2.2 available at /tools/Xilinx/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vmk180/production/2.2/board.xml as part xcvm1802-vsva2197-2mp-e-s specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180:part0:3.0 available at /tools/Xilinx/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vmk180/production/3.0/board.xml as part xcvm1802-vsva2197-2mp-e-s specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180:part0:3.1 available at /tools/Xilinx/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vmk180/production/3.1/board.xml as part xcvm1802-vsva2197-2mp-e-s specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180:part0:3.2 available at /tools/Xilinx/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vmk180/production/3.2/board.xml as part xcvm1802-vsva2197-2mp-e-s specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180_newl:part0:1.0 available at /tools/Xilinx/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vmk180_newl/production/1.0/board.xml as part xcvm1802-vsva2197-2mp-e-s specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180_newl:part0:1.1 available at /tools/Xilinx/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vmk180_newl/production/1.1/board.xml as part xcvm1802-vsva2197-2mp-e-s specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120:part0:1.0 available at /tools/Xilinx/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120/production/1.0/board.xml as part xcvp1202-vsva2785-2mp-e-s specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120:part0:1.1 available at /tools/Xilinx/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120/production/1.1/board.xml as part xcvp1202-vsva2785-2mp-e-s specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120:part0:1.2 available at /tools/Xilinx/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120/production/1.2/board.xml as part xcvp1202-vsva2785-2mp-e-s specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk180:part0:1.0 available at /tools/Xilinx/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk180/production/1.0/board.xml as part xcvp1802-lsvc4072-2mp-e-s specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk180:part0:1.1 available at /tools/Xilinx/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk180/production/1.1/board.xml as part xcvp1802-lsvc4072-2mp-e-s specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk180:part0:1.2 available at /tools/Xilinx/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk180/production/1.2/board.xml as part xcvp1802-lsvc4072-2mp-e-s specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:zc706:part0:1.4 available at /tools/Xilinx/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zc706/1.4/board.xml as part xc7z045ffg900-2 specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu102:part0:3.3 available at /tools/Xilinx/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu102/3.3/board.xml as part xczu9eg-ffvb1156-2-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu102:part0:3.4 available at /tools/Xilinx/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu102/3.4/board.xml as part xczu9eg-ffvb1156-2-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu111:part0:1.2 available at /tools/Xilinx/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu111/1.2/board.xml as part xczu28dr-ffvg1517-2-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu111:part0:1.3 available at /tools/Xilinx/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu111/1.3/board.xml as part xczu28dr-ffvg1517-2-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu111:part0:1.4 available at /tools/Xilinx/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu111/1.4/board.xml as part xczu28dr-ffvg1517-2-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu1275:part0:1.0 available at /tools/Xilinx/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu1275/1.0/board.xml as part xczu29dr-ffvf1760-2-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu1285:part0:1.0 available at /tools/Xilinx/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu1285/1.0/board.xml as part xczu39dr-ffvf1760-2-i specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208:part0:2.0 available at /tools/Xilinx/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208/production/2.0/board.xml as part xczu48dr-fsvg1517-2-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208ld:part0:2.0 available at /tools/Xilinx/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208ld/production/2.0/board.xml as part xczu58dr-fsvg1517-2-i specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216:part0:2.0 available at /tools/Xilinx/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216/production/2.0/board.xml as part xczu49dr-ffvf1760-2-e specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld:part0:2.0 available at /tools/Xilinx/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/production/2.0/board.xml as part xczu59dr-ffvf1760-2-i specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670:part0:2.0 available at /tools/Xilinx/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670/2.0/board.xml as part xczu67dr-fsve1156-2-i specified in board_part file is either invalid or not available
+WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670ld:part0:1.0 available at /tools/Xilinx/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670ld/1.0/board.xml as part xczu57dr-fsve1156-2-i specified in board_part file is either invalid or not available
+Scanning sources...
+Finished scanning sources
+INFO: [IP_Flow 19-234] Refreshing IP repositories
+INFO: [IP_Flow 19-1704] No user IP repositories specified
+INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2024.1/data/ip'.
+open_project: Time (s): cpu = 00:00:24 ; elapsed = 00:00:12 . Memory (MB): peak = 8003.152 ; gain = 490.383 ; free physical = 2421 ; free virtual = 7809
+update_compile_order -fileset sources_1
+exit
+INFO: [Common 17-206] Exiting Vivado at Tue Dec 31 14:32:32 2024...