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View file @ 9811d89d
......@@ -5,9 +5,6 @@ TP_MLP.gen/
TP_MLP.cache/
TP_MLP.sim/
data/
*.xpr
*.wcfg
*.pt
mnist_mlp/data_files/
mnist_mlp/bin/
mnist_mlp/__pycache__/
......
TP_MLP.xpr 0 → 100644
View file @ 9811d89d
<?xml version="1.0" encoding="UTF-8"?>
<!-- Product Version: Vivado v2024.1 (64-bit) -->
<!-- -->
<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -->
<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. -->
<Project Product="Vivado" Version="7" Minor="67" Path="/home/achoul/AI_ON_FPGA/TP_MLP/TP_MLP.xpr">
<DefaultLaunch Dir="$PRUNDIR"/>
<Configuration>
<Option Name="Id" Val="174373bb0f1944ac836362a6a4893920"/>
<Option Name="Part" Val="xc7a35tcpg236-1"/>
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
<Option Name="CompiledLibDirXSim" Val=""/>
<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
<Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
<Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
<Option Name="SimulatorInstallDirModelSim" Val=""/>
<Option Name="SimulatorInstallDirQuesta" Val=""/>
<Option Name="SimulatorInstallDirXcelium" Val=""/>
<Option Name="SimulatorInstallDirVCS" Val=""/>
<Option Name="SimulatorInstallDirRiviera" Val=""/>
<Option Name="SimulatorInstallDirActiveHdl" Val=""/>
<Option Name="SimulatorGccInstallDirModelSim" Val=""/>
<Option Name="SimulatorGccInstallDirQuesta" Val=""/>
<Option Name="SimulatorGccInstallDirXcelium" Val=""/>
<Option Name="SimulatorGccInstallDirVCS" Val=""/>
<Option Name="SimulatorGccInstallDirRiviera" Val=""/>
<Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
<Option Name="SimulatorVersionXsim" Val="2024.1"/>
<Option Name="SimulatorVersionModelSim" Val="2023.2"/>
<Option Name="SimulatorVersionQuesta" Val="2023.2"/>
<Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
<Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
<Option Name="SimulatorVersionRiviera" Val="2023.04"/>
<Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
<Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
<Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
<Option Name="SimulatorGccVersionQuesta" Val="7.4.0"/>
<Option Name="SimulatorGccVersionXcelium" Val="9.3.0"/>
<Option Name="SimulatorGccVersionVCS" Val="9.2.0"/>
<Option Name="SimulatorGccVersionRiviera" Val="9.3.0"/>
<Option Name="SimulatorGccVersionActiveHdl" Val="9.3.0"/>
<Option Name="TargetLanguage" Val="VHDL"/>
<Option Name="SimulatorLanguage" Val="VHDL"/>
<Option Name="BoardPart" Val="xilinx.com:zc702:part0:1.4"/>
<Option Name="ActiveSimSet" Val="sim_1"/>
<Option Name="DefaultLib" Val="xil_defaultlib"/>
<Option Name="ProjectType" Val="Default"/>
<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
<Option Name="IPDefaultOutputPath" Val="$PGENDIR/sources_1"/>
<Option Name="IPCachePermission" Val="read"/>
<Option Name="IPCachePermission" Val="write"/>
<Option Name="EnableCoreContainer" Val="FALSE"/>
<Option Name="EnableResourceEstimation" Val="FALSE"/>
<Option Name="SimCompileState" Val="TRUE"/>
<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
<Option Name="EnableBDX" Val="FALSE"/>
<Option Name="DSABoardId" Val="zc702"/>
<Option Name="WTXSimLaunchSim" Val="805"/>
<Option Name="WTModelSimLaunchSim" Val="0"/>
<Option Name="WTQuestaLaunchSim" Val="0"/>
<Option Name="WTIesLaunchSim" Val="0"/>
<Option Name="WTVcsLaunchSim" Val="0"/>
<Option Name="WTRivieraLaunchSim" Val="0"/>
<Option Name="WTActivehdlLaunchSim" Val="0"/>
<Option Name="WTXSimExportSim" Val="0"/>
<Option Name="WTModelSimExportSim" Val="0"/>
<Option Name="WTQuestaExportSim" Val="0"/>
<Option Name="WTIesExportSim" Val="0"/>
<Option Name="WTVcsExportSim" Val="0"/>
<Option Name="WTRivieraExportSim" Val="0"/>
<Option Name="WTActivehdlExportSim" Val="0"/>
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
<Option Name="XSimRadix" Val="hex"/>
<Option Name="XSimTimeUnit" Val="ns"/>
<Option Name="XSimArrayDisplayLimit" Val="1024"/>
<Option Name="XSimTraceLimit" Val="65536"/>
<Option Name="SimTypes" Val="rtl"/>
<Option Name="SimTypes" Val="bfm"/>
<Option Name="SimTypes" Val="tlm"/>
<Option Name="SimTypes" Val="tlm_dpi"/>
<Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
<Option Name="DcpsUptoDate" Val="TRUE"/>
<Option Name="ClassicSocBoot" Val="FALSE"/>
<Option Name="LocalIPRepoLeafDirName" Val="ip_repo"/>
</Configuration>
<FileSets Version="1" Minor="32">
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
<Filter Type="Srcs"/>
<File Path="$PSRCDIR/sources_1/new/neuron_memory.sv">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/imports/configs/config_pkg.vhd">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="ImportPath" Val="$PPRDIR/mnist_mlp/data_files/configs/config_pkg.vhd"/>
<Attr Name="ImportTime" Val="1727099031"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="std_memory"/>
<Option Name="TopAutoSet" Val="TRUE"/>
</Config>
</FileSet>
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
<Filter Type="Constrs"/>
<Config>
<Option Name="ConstrsType" Val="XDC"/>
</Config>
</FileSet>
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
<Filter Type="Srcs"/>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="std_memory"/>
<Option Name="TopLib" Val="xil_defaultlib"/>
<Option Name="TopAutoSet" Val="TRUE"/>
<Option Name="TransportPathDelay" Val="0"/>
<Option Name="TransportIntDelay" Val="0"/>
<Option Name="SelectedSimModel" Val="rtl"/>
<Option Name="PamDesignTestbench" Val=""/>
<Option Name="PamDutBypassFile" Val="xil_dut_bypass"/>
<Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
<Option Name="PamPseudoTop" Val="pseudo_tb"/>
<Option Name="SrcSet" Val="sources_1"/>
<Option Name="XSimWcfgFile" Val="$PPRDIR/tb_network_behav.wcfg"/>
<Option Name="xsim.simulate.runtime" Val="30000ns"/>
</Config>
</FileSet>
<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
<Filter Type="Utils"/>
<File Path="$PSRCDIR/utils_1/imports/synth_1/network.dcp">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedInSteps" Val="synth_1"/>
<Attr Name="AutoDcp" Val="1"/>
</FileInfo>
</File>
<Config>
<Option Name="TopAutoSet" Val="TRUE"/>
</Config>
</FileSet>
</FileSets>
<Simulators>
<Simulator Name="XSim">
<Option Name="Description" Val="Vivado Simulator"/>
<Option Name="CompiledLib" Val="0"/>
</Simulator>
<Simulator Name="ModelSim">
<Option Name="Description" Val="ModelSim Simulator"/>
</Simulator>
<Simulator Name="Questa">
<Option Name="Description" Val="Questa Advanced Simulator"/>
</Simulator>
<Simulator Name="Xcelium">
<Option Name="Description" Val="Xcelium Parallel Simulator"/>
</Simulator>
<Simulator Name="VCS">
<Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
</Simulator>
<Simulator Name="Riviera">
<Option Name="Description" Val="Riviera-PRO Simulator"/>
</Simulator>
</Simulators>
<Runs Version="1" Minor="22">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" IncrementalCheckpoint="$PSRCDIR/utils_1/imports/synth_1/network.dcp" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" LaunchOptions="-jobs 4 " AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
<Step Id="place_design"/>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design"/>
<Step Id="route_design"/>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="impl_1_copy_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1/impl_1_copy_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1/impl_1_copy_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
<Step Id="place_design"/>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design"/>
<Step Id="route_design"/>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024" CtrlBit="true">
<ReportConfig DisplayName="Timing Summary - Design Initialization" Name="impl_1_copy_1_init_report_timing_summary_0" Spec="report_timing_summary" RunStep="init_design" ReportFile="interface_timing_summary_init.rpt" Version="1" Minor="0" IsDisabled="true">
<ReportConfigOption Name="max_paths" Type="" Value="10"/>
<ReportConfigOption Name="report_unconstrained" Type="" Value="true"/>
<ReportConfigOutputOption Name="pb" Type="string" Value=""/>
<ReportConfigOutputOption Name="rpx" Type="string" Value=""/>
</ReportConfig>
<ReportConfig DisplayName="DRC - Opt Design" Name="impl_1_copy_1_opt_report_drc_0" Spec="report_drc" RunStep="opt_design" ReportFile="interface_drc_opted.rpt" Version="1" Minor="0">
<ReportConfigOption Name="dummy_option" Type="string"/>
<ReportConfigOutputOption Name="pb" Type="string" Value=""/>
<ReportConfigOutputOption Name="rpx" Type="string" Value=""/>
</ReportConfig>
<ReportConfig DisplayName="Timing Summary - Opt Design" Name="impl_1_copy_1_opt_report_timing_summary_0" Spec="report_timing_summary" RunStep="opt_design" ReportFile="interface_timing_summary_opted.rpt" Version="1" Minor="0" IsDisabled="true">
<ReportConfigOption Name="max_paths" Type="" Value="10"/>
<ReportConfigOption Name="report_unconstrained" Type="" Value="true"/>
<ReportConfigOutputOption Name="pb" Type="string" Value=""/>
<ReportConfigOutputOption Name="rpx" Type="string" Value=""/>
</ReportConfig>
<ReportConfig DisplayName="Timing Summary - Power Opt Design" Name="impl_1_copy_1_power_opt_report_timing_summary_0" Spec="report_timing_summary" RunStep="power_opt_design" ReportFile="interface_timing_summary_pwropted.rpt" Version="1" Minor="0" IsDisabled="true">
<ReportConfigOption Name="max_paths" Type="" Value="10"/>
<ReportConfigOption Name="report_unconstrained" Type="" Value="true"/>
<ReportConfigOutputOption Name="pb" Type="string" Value=""/>
<ReportConfigOutputOption Name="rpx" Type="string" Value=""/>
</ReportConfig>
<ReportConfig DisplayName="IO - Place Design" Name="impl_1_copy_1_place_report_io_0" Spec="report_io" RunStep="place_design" ReportFile="interface_io_placed.rpt" Version="1" Minor="0">
<ReportConfigOption Name="dummy_option" Type="string"/>
</ReportConfig>
<ReportConfig DisplayName="Utilization - Place Design" Name="impl_1_copy_1_place_report_utilization_0" Spec="report_utilization" RunStep="place_design" ReportFile="interface_utilization_placed.rpt" Version="1" Minor="0">
<ReportConfigOption Name="dummy_option" Type="string"/>
<ReportConfigOutputOption Name="pb" Type="string" Value=""/>
</ReportConfig>
<ReportConfig DisplayName="Control Sets - Place Design" Name="impl_1_copy_1_place_report_control_sets_0" Spec="report_control_sets" RunStep="place_design" ReportFile="interface_control_sets_placed.rpt" Version="1" Minor="0">
<ReportConfigOption Name="verbose" Type="" Value="true"/>
</ReportConfig>
<ReportConfig DisplayName="Incremental Reuse - Place Design" Name="impl_1_copy_1_place_report_incremental_reuse_0" Spec="report_incremental_reuse" RunStep="place_design" ReportFile="interface_incremental_reuse_pre_placed.rpt.rpt" Version="1" Minor="0" IsDisabled="true">
<ReportConfigOption Name="dummy_option" Type="string"/>
</ReportConfig>
<ReportConfig DisplayName="Incremental Reuse - Place Design" Name="impl_1_copy_1_place_report_incremental_reuse_1" Spec="report_incremental_reuse" RunStep="place_design" ReportFile="interface_incremental_reuse_placed.rpt" Version="1" Minor="0" IsDisabled="true">
<ReportConfigOption Name="dummy_option" Type="string"/>
</ReportConfig>
<ReportConfig DisplayName="Timing Summary - Place Design" Name="impl_1_copy_1_place_report_timing_summary_0" Spec="report_timing_summary" RunStep="place_design" ReportFile="interface_timing_summary_placed.rpt" Version="1" Minor="0" IsDisabled="true">
<ReportConfigOption Name="max_paths" Type="" Value="10"/>
<ReportConfigOption Name="report_unconstrained" Type="" Value="true"/>
<ReportConfigOutputOption Name="pb" Type="string" Value=""/>
<ReportConfigOutputOption Name="rpx" Type="string" Value=""/>
</ReportConfig>
<ReportConfig DisplayName="Timing Summary - Post-Place Power Opt Design" Name="impl_1_copy_1_post_place_power_opt_report_timing_summary_0" Spec="report_timing_summary" RunStep="post_place_power_opt_design" ReportFile="interface_timing_summary_postplace_pwropted.rpt" Version="1" Minor="0" IsDisabled="true">
<ReportConfigOption Name="max_paths" Type="" Value="10"/>
<ReportConfigOption Name="report_unconstrained" Type="" Value="true"/>
<ReportConfigOutputOption Name="pb" Type="string" Value=""/>
<ReportConfigOutputOption Name="rpx" Type="string" Value=""/>
</ReportConfig>
<ReportConfig DisplayName="Timing Summary - Post-Place Phys Opt Design" Name="impl_1_copy_1_phys_opt_report_timing_summary_0" Spec="report_timing_summary" RunStep="phys_opt_design" ReportFile="interface_timing_summary_physopted.rpt" Version="1" Minor="0" IsDisabled="true">
<ReportConfigOption Name="max_paths" Type="" Value="10"/>
<ReportConfigOption Name="report_unconstrained" Type="" Value="true"/>
<ReportConfigOutputOption Name="pb" Type="string" Value=""/>
<ReportConfigOutputOption Name="rpx" Type="string" Value=""/>
</ReportConfig>
<ReportConfig DisplayName="implementation_log" Name="impl_1_copy_1_route_implementation_log_0" Spec="" RunStep="route_design" ReportFile="interface.vdi">
<ReportConfigOption Name="dummy_option" Type="string"/>
</ReportConfig>
<ReportConfig DisplayName="DRC - Route Design" Name="impl_1_copy_1_route_report_drc_0" Spec="report_drc" RunStep="route_design" ReportFile="interface_drc_routed.rpt" Version="1" Minor="0">
<ReportConfigOption Name="dummy_option" Type="string"/>
<ReportConfigOutputOption Name="pb" Type="string" Value=""/>
<ReportConfigOutputOption Name="rpx" Type="string" Value=""/>
</ReportConfig>
<ReportConfig DisplayName="Methodology - Route Design" Name="impl_1_copy_1_route_report_methodology_0" Spec="report_methodology" RunStep="route_design" ReportFile="interface_methodology_drc_routed.rpt" Version="1" Minor="0">
<ReportConfigOption Name="dummy_option" Type="string"/>
<ReportConfigOutputOption Name="pb" Type="string" Value=""/>
<ReportConfigOutputOption Name="rpx" Type="string" Value=""/>
</ReportConfig>
<ReportConfig DisplayName="Power - Route Design" Name="impl_1_copy_1_route_report_power_0" Spec="report_power" RunStep="route_design" ReportFile="interface_power_routed.rpt" Version="1" Minor="0">
<ReportConfigOption Name="dummy_option" Type="string"/>
<ReportConfigOutputOption Name="pb" Type="string" Value=""/>
<ReportConfigOutputOption Name="rpx" Type="string" Value=""/>
</ReportConfig>
<ReportConfig DisplayName="Route Status - Route Design" Name="impl_1_copy_1_route_report_route_status_0" Spec="report_route_status" RunStep="route_design" ReportFile="interface_route_status.rpt" Version="1" Minor="0">
<ReportConfigOption Name="dummy_option" Type="string"/>
<ReportConfigOutputOption Name="pb" Type="string" Value=""/>
</ReportConfig>
<ReportConfig DisplayName="Timing Summary - Route Design" Name="impl_1_copy_1_route_report_timing_summary_0" Spec="report_timing_summary" RunStep="route_design" ReportFile="interface_timing_summary_routed.rpt" Version="1" Minor="0">
<ReportConfigOption Name="max_paths" Type="" Value="10"/>
<ReportConfigOption Name="report_unconstrained" Type="" Value="true"/>
<ReportConfigOutputOption Name="pb" Type="string" Value=""/>
<ReportConfigOutputOption Name="rpx" Type="string" Value=""/>
</ReportConfig>
<ReportConfig DisplayName="Incremental Reuse - Route Design" Name="impl_1_copy_1_route_report_incremental_reuse_0" Spec="report_incremental_reuse" RunStep="route_design" ReportFile="interface_incremental_reuse_routed.rpt" Version="1" Minor="0">
<ReportConfigOption Name="dummy_option" Type="string"/>
</ReportConfig>
<ReportConfig DisplayName="Clock Utilization - Route Design" Name="impl_1_copy_1_route_report_clock_utilization_0" Spec="report_clock_utilization" RunStep="route_design" ReportFile="interface_clock_utilization_routed.rpt" Version="1" Minor="0">
<ReportConfigOption Name="dummy_option" Type="string"/>
</ReportConfig>
<ReportConfig DisplayName="Bus Skew - Route Design" Name="impl_1_copy_1_route_report_bus_skew_0" Spec="report_bus_skew" RunStep="route_design" ReportFile="interface_bus_skew_routed.rpt" Version="1" Minor="1">
<ReportConfigOption Name="warn_on_violation" Type="" Value="true"/>
<ReportConfigOutputOption Name="pb" Type="string" Value=""/>
<ReportConfigOutputOption Name="rpx" Type="string" Value=""/>
</ReportConfig>
<ReportConfig DisplayName="Timing Summary - Post-Route Phys Opt Design" Name="impl_1_copy_1_post_route_phys_opt_report_timing_summary_0" Spec="report_timing_summary" RunStep="post_route_phys_opt_design" ReportFile="interface_timing_summary_postroute_physopted.rpt" Version="1" Minor="0">
<ReportConfigOption Name="max_paths" Type="" Value="10"/>
<ReportConfigOption Name="report_unconstrained" Type="" Value="true"/>
<ReportConfigOption Name="warn_on_violation" Type="" Value="true"/>
<ReportConfigOutputOption Name="pb" Type="string" Value=""/>
<ReportConfigOutputOption Name="rpx" Type="string" Value=""/>
</ReportConfig>
<ReportConfig DisplayName="Bus Skew - Post-Route Phys Opt Design" Name="impl_1_copy_1_post_route_phys_opt_report_bus_skew_0" Spec="report_bus_skew" RunStep="post_route_phys_opt_design" ReportFile="interface_bus_skew_postroute_physopted.rpt" Version="1" Minor="1">
<ReportConfigOption Name="warn_on_violation" Type="" Value="true"/>
<ReportConfigOutputOption Name="pb" Type="string" Value=""/>
<ReportConfigOutputOption Name="rpx" Type="string" Value=""/>
</ReportConfig>
<ReportConfig DisplayName="implementation_log" Name="impl_1_copy_1_bitstream_implementation_log_0" Spec="" RunStep="write_bitstream" ReportFile="interface.vdi">
<ReportConfigOption Name="dummy_option" Type="string"/>
</ReportConfig>
</ReportStrategy>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
</Runs>
<Board>
<Jumpers/>
</Board>
<DashboardSummary Version="1" Minor="0">
<Dashboards>
<Dashboard Name="default_dashboard">
<Gadgets>
<Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
</Gadget>
<Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
</Gadget>
<Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
</Gadget>
<Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
</Gadget>
<Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
<GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
<GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
<GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
</Gadget>
<Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
</Gadget>
</Gadgets>
</Dashboard>
<CurrentDashboard>default_dashboard</CurrentDashboard>
</Dashboards>
</DashboardSummary>
</Project>
vivado.jou
View file @ 9811d89d
......@@ -3,8 +3,8 @@
# SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
# IP Build 5075265 on Wed May 22 21:45:21 MDT 2024
# SharedData Build 5076995 on Wed May 22 18:29:18 MDT 2024
# Start of session at: Tue Dec 31 14:31:47 2024
# Process ID: 54225
# Start of session at: Tue Dec 31 14:36:31 2024
# Process ID: 55168
# Current directory: /home/achoul/AI_ON_FPGA/TP_MLP
# Command line: vivado
# Log file: /home/achoul/AI_ON_FPGA/TP_MLP/vivado.log
......@@ -13,14 +13,31 @@
# Platform :Linuxmint
# Operating System :Linux Mint 21.3
# Processor Detail :Intel(R) Core(TM) i7-6700HQ CPU @ 2.60GHz
# CPU Frequency :2600.000 MHz
# CPU Frequency :3257.715 MHz
# CPU Physical cores:4
# CPU Logical cores :8
# Host memory :16619 MB
# Swap memory :1027 MB
# Total Virtual :17647 MB
# Available Virtual :9328 MB
# Available Virtual :9372 MB
#-----------------------------------------------------------
start_gui
open_project /home/achoul/AI_ON_FPGA/TP_MLP/TP_MLP.xpr
update_compile_order -fileset sources_1
update_compile_order -fileset sim_1
export_ip_user_files -of_objects [get_files /home/achoul/AI_ON_FPGA/TP_MLP/TP_MLP.srcs/sources_1/new/HardTanh.vhd] -no_script -reset -force -quiet
export_ip_user_files -of_objects [get_files /home/achoul/AI_ON_FPGA/TP_MLP/TP_MLP.srcs/sources_1/new/Interface.vhd] -no_script -reset -force -quiet
export_ip_user_files -of_objects [get_files /home/achoul/AI_ON_FPGA/TP_MLP/TP_MLP.srcs/sources_1/new/ReLU.vhd] -no_script -reset -force -quiet
export_ip_user_files -of_objects [get_files /home/achoul/AI_ON_FPGA/TP_MLP/TP_MLP.srcs/sources_1/new/function_pkg.vhd] -no_script -reset -force -quiet
export_ip_user_files -of_objects [get_files /home/achoul/AI_ON_FPGA/TP_MLP/TP_MLP.srcs/sources_1/new/hardmax.vhd] -no_script -reset -force -quiet
export_ip_user_files -of_objects [get_files /home/achoul/AI_ON_FPGA/TP_MLP/TP_MLP.srcs/sources_1/new/layer.vhd] -no_script -reset -force -quiet
export_ip_user_files -of_objects [get_files /home/achoul/AI_ON_FPGA/TP_MLP/TP_MLP.srcs/sources_1/new/network.vhd] -no_script -reset -force -quiet
export_ip_user_files -of_objects [get_files /home/achoul/AI_ON_FPGA/TP_MLP/TP_MLP.srcs/sources_1/new/perceptron.vhd] -no_script -reset -force -quiet
remove_files {/home/achoul/AI_ON_FPGA/TP_MLP/TP_MLP.srcs/sources_1/new/HardTanh.vhd /home/achoul/AI_ON_FPGA/TP_MLP/TP_MLP.srcs/sources_1/new/Interface.vhd /home/achoul/AI_ON_FPGA/TP_MLP/TP_MLP.srcs/sources_1/new/ReLU.vhd /home/achoul/AI_ON_FPGA/TP_MLP/TP_MLP.srcs/sources_1/new/function_pkg.vhd /home/achoul/AI_ON_FPGA/TP_MLP/TP_MLP.srcs/sources_1/new/hardmax.vhd /home/achoul/AI_ON_FPGA/TP_MLP/TP_MLP.srcs/sources_1/new/layer.vhd /home/achoul/AI_ON_FPGA/TP_MLP/TP_MLP.srcs/sources_1/new/network.vhd /home/achoul/AI_ON_FPGA/TP_MLP/TP_MLP.srcs/sources_1/new/perceptron.vhd}
export_ip_user_files -of_objects [get_files /home/achoul/AI_ON_FPGA/TP_MLP/TP_MLP.srcs/sim_1/new/tb_layer.vhd] -no_script -reset -force -quiet
export_ip_user_files -of_objects [get_files /home/achoul/AI_ON_FPGA/TP_MLP/TP_MLP.srcs/sim_1/new/tb_network.vhd] -no_script -reset -force -quiet
export_ip_user_files -of_objects [get_files /home/achoul/AI_ON_FPGA/TP_MLP/TP_MLP.srcs/sim_1/new/tb_perceptron.vhd] -no_script -reset -force -quiet
export_ip_user_files -of_objects [get_files /home/achoul/AI_ON_FPGA/TP_MLP/TP_MLP.srcs/sim_1/new/test_fixe_point.vhd] -no_script -reset -force -quiet
export_ip_user_files -of_objects [get_files /home/achoul/AI_ON_FPGA/TP_MLP/TP_MLP.srcs/sim_1/new/test_text_io.vhd] -no_script -reset -force -quiet
export_ip_user_files -of_objects [get_files /home/achoul/AI_ON_FPGA/TP_MLP/TP_MLP.srcs/sim_1/new/whole_system_tb.vhd] -no_script -reset -force -quiet
remove_files -fileset sim_1 {/home/achoul/AI_ON_FPGA/TP_MLP/TP_MLP.srcs/sim_1/new/tb_layer.vhd /home/achoul/AI_ON_FPGA/TP_MLP/TP_MLP.srcs/sim_1/new/tb_network.vhd /home/achoul/AI_ON_FPGA/TP_MLP/TP_MLP.srcs/sim_1/new/tb_perceptron.vhd /home/achoul/AI_ON_FPGA/TP_MLP/TP_MLP.srcs/sim_1/new/test_fixe_point.vhd /home/achoul/AI_ON_FPGA/TP_MLP/TP_MLP.srcs/sim_1/new/test_text_io.vhd /home/achoul/AI_ON_FPGA/TP_MLP/TP_MLP.srcs/sim_1/new/whole_system_tb.vhd}
vivado.log
View file @ 9811d89d
......@@ -3,8 +3,8 @@
# SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
# IP Build 5075265 on Wed May 22 21:45:21 MDT 2024
# SharedData Build 5076995 on Wed May 22 18:29:18 MDT 2024
# Start of session at: Tue Dec 31 14:31:47 2024
# Process ID: 54225
# Start of session at: Tue Dec 31 14:36:31 2024
# Process ID: 55168
# Current directory: /home/achoul/AI_ON_FPGA/TP_MLP
# Command line: vivado
# Log file: /home/achoul/AI_ON_FPGA/TP_MLP/vivado.log
......@@ -13,13 +13,13 @@
# Platform :Linuxmint
# Operating System :Linux Mint 21.3
# Processor Detail :Intel(R) Core(TM) i7-6700HQ CPU @ 2.60GHz
# CPU Frequency :2600.000 MHz
# CPU Frequency :3257.715 MHz
# CPU Physical cores:4
# CPU Logical cores :8
# Host memory :16619 MB
# Swap memory :1027 MB
# Total Virtual :17647 MB
# Available Virtual :9328 MB
# Available Virtual :9372 MB
#-----------------------------------------------------------
start_gui
open_project /home/achoul/AI_ON_FPGA/TP_MLP/TP_MLP.xpr
......@@ -84,12 +84,43 @@ WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216:part0:2.0 availab
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld:part0:2.0 available at /tools/Xilinx/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/production/2.0/board.xml as part xczu59dr-ffvf1760-2-i specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670:part0:2.0 available at /tools/Xilinx/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670/2.0/board.xml as part xczu67dr-fsve1156-2-i specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670ld:part0:1.0 available at /tools/Xilinx/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670ld/1.0/board.xml as part xczu57dr-fsve1156-2-i specified in board_part file is either invalid or not available
CRITICAL WARNING: [Project 1-19] Could not find the file '/home/achoul/AI_ON_FPGA/TP_MLP/TP_MLP.srcs/sources_1/new/function_pkg.vhd'.
CRITICAL WARNING: [Project 1-19] Could not find the file '/home/achoul/AI_ON_FPGA/TP_MLP/TP_MLP.srcs/sources_1/new/HardTanh.vhd'.
CRITICAL WARNING: [Project 1-19] Could not find the file '/home/achoul/AI_ON_FPGA/TP_MLP/TP_MLP.srcs/sources_1/new/ReLU.vhd'.
CRITICAL WARNING: [Project 1-19] Could not find the file '/home/achoul/AI_ON_FPGA/TP_MLP/TP_MLP.srcs/sources_1/new/hardmax.vhd'.
CRITICAL WARNING: [Project 1-19] Could not find the file '/home/achoul/AI_ON_FPGA/TP_MLP/TP_MLP.srcs/sources_1/new/layer.vhd'.
CRITICAL WARNING: [Project 1-19] Could not find the file '/home/achoul/AI_ON_FPGA/TP_MLP/TP_MLP.srcs/sources_1/new/network.vhd'.
CRITICAL WARNING: [Project 1-19] Could not find the file '/home/achoul/AI_ON_FPGA/TP_MLP/TP_MLP.srcs/sources_1/new/perceptron.vhd'.
CRITICAL WARNING: [Project 1-19] Could not find the file '/home/achoul/AI_ON_FPGA/TP_MLP/TP_MLP.srcs/sources_1/new/Interface.vhd'.
CRITICAL WARNING: [Project 1-19] Could not find the file '/home/achoul/AI_ON_FPGA/TP_MLP/TP_MLP.srcs/sim_1/new/tb_layer.vhd'.
CRITICAL WARNING: [Project 1-19] Could not find the file '/home/achoul/AI_ON_FPGA/TP_MLP/TP_MLP.srcs/sim_1/new/tb_network.vhd'.
CRITICAL WARNING: [Project 1-19] Could not find the file '/home/achoul/AI_ON_FPGA/TP_MLP/TP_MLP.srcs/sim_1/new/whole_system_tb.vhd'.
CRITICAL WARNING: [Project 1-19] Could not find the file '/home/achoul/AI_ON_FPGA/TP_MLP/TP_MLP.srcs/sim_1/new/test_fixe_point.vhd'.
CRITICAL WARNING: [Project 1-19] Could not find the file '/home/achoul/AI_ON_FPGA/TP_MLP/TP_MLP.srcs/sim_1/new/test_text_io.vhd'.
CRITICAL WARNING: [Project 1-19] Could not find the file '/home/achoul/AI_ON_FPGA/TP_MLP/TP_MLP.srcs/sim_1/new/tb_perceptron.vhd'.
Scanning sources...
Finished scanning sources
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2024.1/data/ip'.
open_project: Time (s): cpu = 00:00:24 ; elapsed = 00:00:12 . Memory (MB): peak = 8003.152 ; gain = 490.383 ; free physical = 2421 ; free virtual = 7809
open_project: Time (s): cpu = 00:00:24 ; elapsed = 00:00:12 . Memory (MB): peak = 7983.617 ; gain = 478.625 ; free physical = 2460 ; free virtual = 7850
update_compile_order -fileset sources_1
update_compile_order -fileset sim_1
export_ip_user_files -of_objects [get_files /home/achoul/AI_ON_FPGA/TP_MLP/TP_MLP.srcs/sources_1/new/HardTanh.vhd] -no_script -reset -force -quiet
export_ip_user_files -of_objects [get_files /home/achoul/AI_ON_FPGA/TP_MLP/TP_MLP.srcs/sources_1/new/Interface.vhd] -no_script -reset -force -quiet
export_ip_user_files -of_objects [get_files /home/achoul/AI_ON_FPGA/TP_MLP/TP_MLP.srcs/sources_1/new/ReLU.vhd] -no_script -reset -force -quiet
export_ip_user_files -of_objects [get_files /home/achoul/AI_ON_FPGA/TP_MLP/TP_MLP.srcs/sources_1/new/function_pkg.vhd] -no_script -reset -force -quiet
export_ip_user_files -of_objects [get_files /home/achoul/AI_ON_FPGA/TP_MLP/TP_MLP.srcs/sources_1/new/hardmax.vhd] -no_script -reset -force -quiet
export_ip_user_files -of_objects [get_files /home/achoul/AI_ON_FPGA/TP_MLP/TP_MLP.srcs/sources_1/new/layer.vhd] -no_script -reset -force -quiet
export_ip_user_files -of_objects [get_files /home/achoul/AI_ON_FPGA/TP_MLP/TP_MLP.srcs/sources_1/new/network.vhd] -no_script -reset -force -quiet
export_ip_user_files -of_objects [get_files /home/achoul/AI_ON_FPGA/TP_MLP/TP_MLP.srcs/sources_1/new/perceptron.vhd] -no_script -reset -force -quiet
remove_files {/home/achoul/AI_ON_FPGA/TP_MLP/TP_MLP.srcs/sources_1/new/HardTanh.vhd /home/achoul/AI_ON_FPGA/TP_MLP/TP_MLP.srcs/sources_1/new/Interface.vhd /home/achoul/AI_ON_FPGA/TP_MLP/TP_MLP.srcs/sources_1/new/ReLU.vhd /home/achoul/AI_ON_FPGA/TP_MLP/TP_MLP.srcs/sources_1/new/function_pkg.vhd /home/achoul/AI_ON_FPGA/TP_MLP/TP_MLP.srcs/sources_1/new/hardmax.vhd /home/achoul/AI_ON_FPGA/TP_MLP/TP_MLP.srcs/sources_1/new/layer.vhd /home/achoul/AI_ON_FPGA/TP_MLP/TP_MLP.srcs/sources_1/new/network.vhd /home/achoul/AI_ON_FPGA/TP_MLP/TP_MLP.srcs/sources_1/new/perceptron.vhd}
export_ip_user_files -of_objects [get_files /home/achoul/AI_ON_FPGA/TP_MLP/TP_MLP.srcs/sim_1/new/tb_layer.vhd] -no_script -reset -force -quiet
export_ip_user_files -of_objects [get_files /home/achoul/AI_ON_FPGA/TP_MLP/TP_MLP.srcs/sim_1/new/tb_network.vhd] -no_script -reset -force -quiet
export_ip_user_files -of_objects [get_files /home/achoul/AI_ON_FPGA/TP_MLP/TP_MLP.srcs/sim_1/new/tb_perceptron.vhd] -no_script -reset -force -quiet
export_ip_user_files -of_objects [get_files /home/achoul/AI_ON_FPGA/TP_MLP/TP_MLP.srcs/sim_1/new/test_fixe_point.vhd] -no_script -reset -force -quiet
export_ip_user_files -of_objects [get_files /home/achoul/AI_ON_FPGA/TP_MLP/TP_MLP.srcs/sim_1/new/test_text_io.vhd] -no_script -reset -force -quiet
export_ip_user_files -of_objects [get_files /home/achoul/AI_ON_FPGA/TP_MLP/TP_MLP.srcs/sim_1/new/whole_system_tb.vhd] -no_script -reset -force -quiet
remove_files -fileset sim_1 {/home/achoul/AI_ON_FPGA/TP_MLP/TP_MLP.srcs/sim_1/new/tb_layer.vhd /home/achoul/AI_ON_FPGA/TP_MLP/TP_MLP.srcs/sim_1/new/tb_network.vhd /home/achoul/AI_ON_FPGA/TP_MLP/TP_MLP.srcs/sim_1/new/tb_perceptron.vhd /home/achoul/AI_ON_FPGA/TP_MLP/TP_MLP.srcs/sim_1/new/test_fixe_point.vhd /home/achoul/AI_ON_FPGA/TP_MLP/TP_MLP.srcs/sim_1/new/test_text_io.vhd /home/achoul/AI_ON_FPGA/TP_MLP/TP_MLP.srcs/sim_1/new/whole_system_tb.vhd}
exit
INFO: [Common 17-206] Exiting Vivado at Tue Dec 31 14:32:32 2024...
INFO: [Common 17-206] Exiting Vivado at Tue Dec 31 14:37:46 2024...
vivado_54225.backup.jou 0 → 100644
View file @ 9811d89d
#-----------------------------------------------------------
# Vivado v2024.1 (64-bit)
# SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
# IP Build 5075265 on Wed May 22 21:45:21 MDT 2024
# SharedData Build 5076995 on Wed May 22 18:29:18 MDT 2024
# Start of session at: Tue Dec 31 14:31:47 2024
# Process ID: 54225
# Current directory: /home/achoul/AI_ON_FPGA/TP_MLP
# Command line: vivado
# Log file: /home/achoul/AI_ON_FPGA/TP_MLP/vivado.log
# Journal file: /home/achoul/AI_ON_FPGA/TP_MLP/vivado.jou
# Running On :Gros-PC-PT
# Platform :Linuxmint
# Operating System :Linux Mint 21.3
# Processor Detail :Intel(R) Core(TM) i7-6700HQ CPU @ 2.60GHz
# CPU Frequency :2600.000 MHz
# CPU Physical cores:4
# CPU Logical cores :8
# Host memory :16619 MB
# Swap memory :1027 MB
# Total Virtual :17647 MB
# Available Virtual :9328 MB
#-----------------------------------------------------------
start_gui
open_project /home/achoul/AI_ON_FPGA/TP_MLP/TP_MLP.xpr
update_compile_order -fileset sources_1
vivado_54225.backup.log 0 → 100644
View file @ 9811d89d
#-----------------------------------------------------------
# Vivado v2024.1 (64-bit)
# SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
# IP Build 5075265 on Wed May 22 21:45:21 MDT 2024
# SharedData Build 5076995 on Wed May 22 18:29:18 MDT 2024
# Start of session at: Tue Dec 31 14:31:47 2024
# Process ID: 54225
# Current directory: /home/achoul/AI_ON_FPGA/TP_MLP
# Command line: vivado
# Log file: /home/achoul/AI_ON_FPGA/TP_MLP/vivado.log
# Journal file: /home/achoul/AI_ON_FPGA/TP_MLP/vivado.jou
# Running On :Gros-PC-PT
# Platform :Linuxmint
# Operating System :Linux Mint 21.3
# Processor Detail :Intel(R) Core(TM) i7-6700HQ CPU @ 2.60GHz
# CPU Frequency :2600.000 MHz
# CPU Physical cores:4
# CPU Logical cores :8
# Host memory :16619 MB
# Swap memory :1027 MB
# Total Virtual :17647 MB
# Available Virtual :9328 MB
#-----------------------------------------------------------
start_gui
open_project /home/achoul/AI_ON_FPGA/TP_MLP/TP_MLP.xpr
WARNING: [Board 49-26] cannot add Board Part xilinx.com:kc705:part0:1.6 available at /tools/Xilinx/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kc705/1.6/board.xml as part xc7k325tffg900-2 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu105:part0:1.6 available at /tools/Xilinx/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu105/1.6/board.xml as part xcku040-ffva1156-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu105:part0:1.7 available at /tools/Xilinx/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu105/1.7/board.xml as part xcku040-ffva1156-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu1500:part0:1.2 available at /tools/Xilinx/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu1500/1.2/board.xml as part xcku115-flvb2104-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vc707:part0:1.4 available at /tools/Xilinx/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vc707/1.4/board.xml as part xc7vx485tffg1761-2 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vc709:part0:1.8 available at /tools/Xilinx/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vc709/1.8/board.xml as part xc7vx690tffg1761-2 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190:part0:2.2 available at /tools/Xilinx/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vck190/production/2.2/board.xml as part xcvc1902-vsva2197-2mp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190:part0:3.0 available at /tools/Xilinx/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vck190/production/3.0/board.xml as part xcvc1902-vsva2197-2mp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190:part0:3.1 available at /tools/Xilinx/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vck190/production/3.1/board.xml as part xcvc1902-vsva2197-2mp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190:part0:3.2 available at /tools/Xilinx/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vck190/production/3.2/board.xml as part xcvc1902-vsva2197-2mp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190:part0:3.3 available at /tools/Xilinx/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vck190/production/3.3/board.xml as part xcvc1902-vsva2197-2mp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190_newl:part0:1.0 available at /tools/Xilinx/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vck190_newl/production/1.0/board.xml as part xcvc1902-vsva2197-2mp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190_newl:part0:1.1 available at /tools/Xilinx/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vck190_newl/production/1.1/board.xml as part xcvc1902-vsva2197-2mp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190_newl:part0:1.2 available at /tools/Xilinx/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vck190_newl/production/1.2/board.xml as part xcvc1902-vsva2197-2mp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu108:part0:1.6 available at /tools/Xilinx/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu108/1.6/board.xml as part xcvu095-ffva2104-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu108:part0:1.7 available at /tools/Xilinx/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu108/1.7/board.xml as part xcvu095-ffva2104-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu110:part0:1.4 available at /tools/Xilinx/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu110/1.4/board.xml as part xcvu190-flgc2104-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu118:part0:2.0 available at /tools/Xilinx/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu118/2.0/board.xml as part xcvu9p-flga2104-2l-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu118:part0:2.3 available at /tools/Xilinx/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu118/2.3/board.xml as part xcvu9p-flga2104-2l-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu118:part0:2.4 available at /tools/Xilinx/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu118/2.4/board.xml as part xcvu9p-flga2104-2l-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu129:part0:1.0 available at /tools/Xilinx/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu129/production/1.0/board.xml as part xcvu29p-fsga2577-2l-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu1525:part0:1.3 available at /tools/Xilinx/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu1525/1.3/board.xml as part xcvu9p-fsgd2104-2l-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280:part0:1.0 available at /tools/Xilinx/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/production/1.0/board.xml as part xcve2802-vsvh1760-2mp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280:part0:1.1 available at /tools/Xilinx/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/production/1.1/board.xml as part xcve2802-vsvh1760-2mp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280:part0:1.2 available at /tools/Xilinx/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/production/1.2/board.xml as part xcve2802-vsvh1760-2mp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280_es:part0:1.0 available at /tools/Xilinx/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/es/rev_a/1.0/board.xml as part xcve2802-vsvh1760-2lp-e-s-es1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280_es:part0:1.1 available at /tools/Xilinx/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/es/rev_a/1.1/board.xml as part xcve2802-vsvh1760-2lp-e-s-es1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280_es_revb:part0:1.0 available at /tools/Xilinx/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/es/rev_b/1.0/board.xml as part xcve2802-vsvh1760-2mp-e-s-es1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280_es_revb:part0:1.1 available at /tools/Xilinx/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/es/rev_b/1.1/board.xml as part xcve2802-vsvh1760-2mp-e-s-es1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vermeo_t1_mpsoc:part0:1.0 available at /tools/Xilinx/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vermeo_t1_mpsoc/1.0/board.xml as part xczu19eg-ffvd1760-2l-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vermeo_t1_rfsoc:part0:1.0 available at /tools/Xilinx/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vermeo_t1_rfsoc/1.0/board.xml as part xczu21dr-ffvd1156-2l-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vhk158:part0:1.0 available at /tools/Xilinx/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vhk158/production/1.0/board.xml as part xcvh1582-vsva3697-2mp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vhk158:part0:1.1 available at /tools/Xilinx/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vhk158/production/1.1/board.xml as part xcvh1582-vsva3697-2mp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vhk158_es:part0:1.0 available at /tools/Xilinx/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vhk158/es/1.0/board.xml as part xcvh1582-vsva3697-2mp-e-s-es1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vhk158_es:part0:1.1 available at /tools/Xilinx/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vhk158/es/1.1/board.xml as part xcvh1582-vsva3697-2mp-e-s-es1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180:part0:2.2 available at /tools/Xilinx/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vmk180/production/2.2/board.xml as part xcvm1802-vsva2197-2mp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180:part0:3.0 available at /tools/Xilinx/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vmk180/production/3.0/board.xml as part xcvm1802-vsva2197-2mp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180:part0:3.1 available at /tools/Xilinx/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vmk180/production/3.1/board.xml as part xcvm1802-vsva2197-2mp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180:part0:3.2 available at /tools/Xilinx/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vmk180/production/3.2/board.xml as part xcvm1802-vsva2197-2mp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180_newl:part0:1.0 available at /tools/Xilinx/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vmk180_newl/production/1.0/board.xml as part xcvm1802-vsva2197-2mp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180_newl:part0:1.1 available at /tools/Xilinx/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vmk180_newl/production/1.1/board.xml as part xcvm1802-vsva2197-2mp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120:part0:1.0 available at /tools/Xilinx/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120/production/1.0/board.xml as part xcvp1202-vsva2785-2mp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120:part0:1.1 available at /tools/Xilinx/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120/production/1.1/board.xml as part xcvp1202-vsva2785-2mp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120:part0:1.2 available at /tools/Xilinx/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120/production/1.2/board.xml as part xcvp1202-vsva2785-2mp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk180:part0:1.0 available at /tools/Xilinx/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk180/production/1.0/board.xml as part xcvp1802-lsvc4072-2mp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk180:part0:1.1 available at /tools/Xilinx/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk180/production/1.1/board.xml as part xcvp1802-lsvc4072-2mp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk180:part0:1.2 available at /tools/Xilinx/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk180/production/1.2/board.xml as part xcvp1802-lsvc4072-2mp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zc706:part0:1.4 available at /tools/Xilinx/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zc706/1.4/board.xml as part xc7z045ffg900-2 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu102:part0:3.3 available at /tools/Xilinx/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu102/3.3/board.xml as part xczu9eg-ffvb1156-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu102:part0:3.4 available at /tools/Xilinx/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu102/3.4/board.xml as part xczu9eg-ffvb1156-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu111:part0:1.2 available at /tools/Xilinx/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu111/1.2/board.xml as part xczu28dr-ffvg1517-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu111:part0:1.3 available at /tools/Xilinx/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu111/1.3/board.xml as part xczu28dr-ffvg1517-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu111:part0:1.4 available at /tools/Xilinx/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu111/1.4/board.xml as part xczu28dr-ffvg1517-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu1275:part0:1.0 available at /tools/Xilinx/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu1275/1.0/board.xml as part xczu29dr-ffvf1760-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu1285:part0:1.0 available at /tools/Xilinx/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu1285/1.0/board.xml as part xczu39dr-ffvf1760-2-i specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208:part0:2.0 available at /tools/Xilinx/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208/production/2.0/board.xml as part xczu48dr-fsvg1517-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208ld:part0:2.0 available at /tools/Xilinx/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208ld/production/2.0/board.xml as part xczu58dr-fsvg1517-2-i specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216:part0:2.0 available at /tools/Xilinx/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216/production/2.0/board.xml as part xczu49dr-ffvf1760-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld:part0:2.0 available at /tools/Xilinx/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/production/2.0/board.xml as part xczu59dr-ffvf1760-2-i specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670:part0:2.0 available at /tools/Xilinx/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670/2.0/board.xml as part xczu67dr-fsve1156-2-i specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670ld:part0:1.0 available at /tools/Xilinx/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670ld/1.0/board.xml as part xczu57dr-fsve1156-2-i specified in board_part file is either invalid or not available
Scanning sources...
Finished scanning sources
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2024.1/data/ip'.
open_project: Time (s): cpu = 00:00:24 ; elapsed = 00:00:12 . Memory (MB): peak = 8003.152 ; gain = 490.383 ; free physical = 2421 ; free virtual = 7809
update_compile_order -fileset sources_1
exit
INFO: [Common 17-206] Exiting Vivado at Tue Dec 31 14:32:32 2024...