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This is the official Low Side Synchronous Buck converter Gitlab
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Linux Module for : 1) R/W mmio registers. 2) Context change send info. 3) Interrupts handler.
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MATANA Implementation on Chipyard (Rocket-Chip RISC-V Softcore processor) on ML605 board
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Code source of the Monte-Carlo Tree search, published at CP2021
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radelin_thesis / openabe_opti
GNU Affero General Public License v3.0Updated -
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Philippe Hérail / RDDLSim-Custom
Apache License 2.0Customized rddlsim version for my personal use
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REHAD / Rehad-Orca
OtherModification of RISC-V softcore processor Orca.
REHAD: Using Low-Frequency Reconfigurable Hardware for Cache Side-Channel Attacks Detection. Run on ML605 evaluation board with UART 115200.
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Generate ROM with attacks for Rehad-Orca.
For synthesis, place mem.hex in ip/idram/src/input. [Request GCC cross compiler (RV32IM).] For bitsteam, replace BRAM content of myorca.bit. [Request Xilinx ISE setup and liscence.]Updated -
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Clone of https://git.openrobots.org/projects/robotpkg with branches prepared for the CI of other projects
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Clone of https://git.openrobots.org/projects/robotpkg-wip with branches prepared for the CI of other projects
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