From cd13dd0192ecae16ab87ed0b2e043f085424e723 Mon Sep 17 00:00:00 2001
From: Ayoub Farah Hassan <afarahhass@laas.fr>
Date: Wed, 13 Jul 2022 10:08:36 +0000
Subject: [PATCH] Revision of HRTIM. Rewrote hrtim driver with LL APIs. Added
Up-down mode (center aligned PWM) for buck, boost and independent mode.
Corrected initialization errors for independent mode.
---
.../public_api/HardwareConfiguration.cpp | 26 +
.../zephyr/public_api/HardwareConfiguration.h | 6 +
.../zephyr/src/hrtim_configuration.cpp | 55 +
.../zephyr/src/hrtim_configuration.h | 21 +
.../zephyr/public_include/hrtim.h | 21 +-
.../zephyr/public_include/leg.h | 11 +
.../zephyr/src/hrtim_common.c | 37 +
.../src/voltage_mode/hrtim_voltage_mode.c | 702 +++++++----
.../src/voltage_mode/hrtim_voltage_mode.h | 1074 +++++++++++------
.../src/voltage_mode/owntech_leg_driver.cpp | 67 +-
10 files changed, 1460 insertions(+), 560 deletions(-)
diff --git a/zephyr/modules/owntech_hardware_configuration/zephyr/public_api/HardwareConfiguration.cpp b/zephyr/modules/owntech_hardware_configuration/zephyr/public_api/HardwareConfiguration.cpp
index 62d8423..1a7047a 100644
--- a/zephyr/modules/owntech_hardware_configuration/zephyr/public_api/HardwareConfiguration.cpp
+++ b/zephyr/modules/owntech_hardware_configuration/zephyr/public_api/HardwareConfiguration.cpp
@@ -22,6 +22,7 @@
*
* @author Clément Foucher <clement.foucher@laas.fr>
* @author Luiz Villa <luiz.villa@laas.fr>
+ * @author Ayoub Farah Hassan <ayoub.farah-hassan@laas.fr>
*/
@@ -130,26 +131,51 @@ void HardwareConfiguration::initInterleavedBuckMode()
hrtim_init_interleaved_buck_mode();
}
+void HardwareConfiguration::initInterleavedBuckModeCenterAligned()
+{
+ hrtim_init_interleaved_buck_mode_center_aligned();
+}
+
void HardwareConfiguration::initInterleavedBoostMode()
{
hrtim_init_interleaved_boost_mode();
}
+void HardwareConfiguration::initInterleavedBoostModeCenterAligned()
+{
+ hrtim_init_interleaved_boost_mode_center_aligned();
+}
+
void HardwareConfiguration::initFullBridgeBuckMode()
{
hrtim_init_interleaved_buck_mode();
}
+void HardwareConfiguration::initFullBridgeBuckModeCenterAligned()
+{
+ hrtim_init_interleaved_buck_mode_center_aligned();
+}
+
void HardwareConfiguration::initFullBridgeBoostMode()
{
hrtim_init_interleaved_boost_mode();
}
+void HardwareConfiguration::initFullBridgeBoostModeCenterAligned()
+{
+ hrtim_init_interleaved_boost_mode_center_aligned();
+}
+
void HardwareConfiguration::initIndependentMode(bool leg1_buck_mode, bool leg2_buck_mode)
{
hrtim_init_independent_mode(leg1_buck_mode, leg2_buck_mode);
}
+void HardwareConfiguration::initIndependentModeCenterAligned(bool leg1_buck_mode, bool leg2_buck_mode)
+{
+ hrtim_init_independent_mode_center_aligned(leg1_buck_mode, leg2_buck_mode);
+}
+
void HardwareConfiguration::setInterleavedDutyCycle(float32_t duty_cycle)
{
hrtim_interleaved_pwm_update(duty_cycle);
diff --git a/zephyr/modules/owntech_hardware_configuration/zephyr/public_api/HardwareConfiguration.h b/zephyr/modules/owntech_hardware_configuration/zephyr/public_api/HardwareConfiguration.h
index 48be111..1ae42af 100644
--- a/zephyr/modules/owntech_hardware_configuration/zephyr/public_api/HardwareConfiguration.h
+++ b/zephyr/modules/owntech_hardware_configuration/zephyr/public_api/HardwareConfiguration.h
@@ -22,6 +22,7 @@
*
* @author Clément Foucher <clement.foucher@laas.fr>
* @author Luiz Villa <luiz.villa@laas.fr>
+ * @author Ayoub Farah Hassan <ayoub.farah-hassan@laas.fr>
*/
@@ -78,10 +79,15 @@ public:
// Power converter
static void initInterleavedBuckMode();
+ static void initInterleavedBuckModeCenterAligned();
static void initInterleavedBoostMode();
+ static void initInterleavedBoostModeCenterAligned();
static void initFullBridgeBuckMode();
+ static void initFullBridgeBuckModeCenterAligned();
static void initFullBridgeBoostMode();
+ static void initFullBridgeBoostModeCenterAligned();
static void initIndependentMode(bool leg1_buck_mode, bool leg2_buck_mode);
+ static void initIndependentModeCenterAligned(bool leg1_buck_mode, bool leg2_buck_mode);
static void setInterleavedDutyCycle(float32_t duty_cycle);
static void setFullBridgeDutyCycle(float32_t duty_cycle);
diff --git a/zephyr/modules/owntech_hardware_configuration/zephyr/src/hrtim_configuration.cpp b/zephyr/modules/owntech_hardware_configuration/zephyr/src/hrtim_configuration.cpp
index f54a035..521bea9 100644
--- a/zephyr/modules/owntech_hardware_configuration/zephyr/src/hrtim_configuration.cpp
+++ b/zephyr/modules/owntech_hardware_configuration/zephyr/src/hrtim_configuration.cpp
@@ -21,6 +21,7 @@
* @date 2022
* @author Luiz Villa <luiz.villa@laas.fr>
* @author Clément Foucher <clement.foucher@laas.fr>
+ * @author Ayoub Farah Hassan <ayoub.farah-hassan@laas.fr>
*/
@@ -60,6 +61,19 @@ void hrtim_init_interleaved_buck_mode()
pwm_high_pulse_width = pwm_period * HIGH_DUTY;
}
+/**
+ * This function initializes both legs in buck mode in up-down mode
+ */
+void hrtim_init_interleaved_buck_mode_center_aligned()
+{
+ hrtim_init_voltage_buck_center_aligned();
+
+ pwm_period = leg_period();
+ pwm_phase_shift = pwm_period;
+ pwm_low_pulse_width = pwm_period * LOW_DUTY;
+ pwm_high_pulse_width = pwm_period * HIGH_DUTY;
+}
+
/**
* This function initializes both legs in boost mode
*/
@@ -73,6 +87,16 @@ void hrtim_init_interleaved_boost_mode()
pwm_high_pulse_width = pwm_period * HIGH_DUTY;
}
+void hrtim_init_interleaved_boost_mode_center_aligned()
+{
+ hrtim_init_voltage_boost_center_aligned();
+
+ pwm_period = leg_period();
+ pwm_phase_shift = pwm_period;
+ pwm_low_pulse_width = pwm_period * LOW_DUTY;
+ pwm_high_pulse_width = pwm_period * HIGH_DUTY;
+}
+
/**
* This leg initializes each leg independently. It receives the modes of each leg and triggers them accordingly.
*/
@@ -85,6 +109,12 @@ void hrtim_init_independent_mode(bool leg1_buck_mode, bool leg2_buck_mode)
else if (!leg1_buck_mode && leg2_buck_mode){
hrtim_init_voltage_leg1_boost_leg2_buck();
}
+ else if (leg1_buck_mode && leg2_buck_mode){
+ hrtim_init_voltage_buck();
+ }
+ else if (!leg1_buck_mode && !leg2_buck_mode){
+ hrtim_init_voltage_boost();
+ }
pwm_period = leg_period();
pwm_phase_shift = pwm_period / 2;
@@ -92,6 +122,31 @@ void hrtim_init_independent_mode(bool leg1_buck_mode, bool leg2_buck_mode)
pwm_high_pulse_width = pwm_period * HIGH_DUTY;
}
+/**
+ * This leg initializes each leg independently. It receives the modes of each leg and triggers them accordingly.
+ * The counting mode is set to up-down (center aligned).
+ */
+void hrtim_init_independent_mode_center_aligned(bool leg1_buck_mode, bool leg2_buck_mode)
+{
+ // High resolution timer initialization
+ if (leg1_buck_mode && !leg2_buck_mode){
+ hrtim_init_voltage_leg1_buck_leg2_boost_center_aligned();
+ }
+ else if (!leg1_buck_mode && leg2_buck_mode){
+ hrtim_init_voltage_leg1_boost_leg2_buck_center_aligned();
+ }
+ else if (leg1_buck_mode && leg2_buck_mode){
+ hrtim_init_voltage_buck_center_aligned();
+ }
+ else if (!leg1_buck_mode && !leg2_buck_mode){
+ hrtim_init_voltage_boost_center_aligned();
+ }
+
+ pwm_period = leg_period();
+ pwm_phase_shift = pwm_period;
+ pwm_low_pulse_width = pwm_period * LOW_DUTY;
+ pwm_high_pulse_width = pwm_period * HIGH_DUTY;
+}
/**
diff --git a/zephyr/modules/owntech_hardware_configuration/zephyr/src/hrtim_configuration.h b/zephyr/modules/owntech_hardware_configuration/zephyr/src/hrtim_configuration.h
index f980e81..83614f5 100644
--- a/zephyr/modules/owntech_hardware_configuration/zephyr/src/hrtim_configuration.h
+++ b/zephyr/modules/owntech_hardware_configuration/zephyr/src/hrtim_configuration.h
@@ -36,18 +36,39 @@
*/
void hrtim_init_interleaved_buck_mode();
+/**
+ * @brief This function initializes the converter in interleaved buck mode
+ * with the input on the high side and the output on the low side. The counting mode
+ * is set to up-down (center aligned).
+ */
+void hrtim_init_interleaved_buck_mode_center_aligned();
+
/**
* @brief This function initializes the converter in interleaved boost mode
* with the input on the low side and the output on the high side
*/
void hrtim_init_interleaved_boost_mode();
+/**
+ * @brief This function initializes the converter in interleaved boost mode
+ * with the input on the low side and the output on the high side. The counting mode
+ * is set to up-down (center aligned).
+ */
+void hrtim_init_interleaved_boost_mode_center_aligned();
+
/**
* @brief This function initializes the converter in independent mode
* the user must define the mode for each leg separetely
*/
void hrtim_init_independent_mode(bool leg1_buck_mode, bool leg2_buck_mode);
+/**
+ * @brief This function initializes the converter in independent mode
+ * the user must define the mode for each leg separetely. The counting mode
+ * is set to up-down (center aligned).
+ */
+void hrtim_init_independent_mode_center_aligned(bool leg1_buck_mode, bool leg2_buck_mode);
+
/**
* @brief This function transfer the calculated PWM value to the
* HRTIM peripheral and make sure it is between saturation
diff --git a/zephyr/modules/owntech_hrtim_driver/zephyr/public_include/hrtim.h b/zephyr/modules/owntech_hrtim_driver/zephyr/public_include/hrtim.h
index 4826336..18f45db 100644
--- a/zephyr/modules/owntech_hrtim_driver/zephyr/public_include/hrtim.h
+++ b/zephyr/modules/owntech_hrtim_driver/zephyr/public_include/hrtim.h
@@ -20,6 +20,7 @@
/**
* @author Clément Foucher <clement.foucher@laas.fr>
* @author Luiz Villa <luiz.villa@laas.fr>
+ * @author Ayoub Farah Hassan <ayoub.farah-hassan@laas.fr>
*/
#ifndef HRTIM_H_
@@ -28,6 +29,8 @@
#include <stdint.h>
+#include <stm32_ll_hrtim.h>
+
#ifdef __cplusplus
extern "C" {
@@ -53,15 +56,15 @@ typedef unsigned int hrtim_t;
* @brief HRTIM timing units definition
*/
typedef enum {
- TIMA,
- TIMB,
- TIMC,
- TIMD,
- TIME,
+ TIMA = LL_HRTIM_TIMER_A,
+ TIMB = LL_HRTIM_TIMER_B,
+ TIMC = LL_HRTIM_TIMER_C,
+ TIMD = LL_HRTIM_TIMER_D,
+ TIME = LL_HRTIM_TIMER_E,
#if (HRTIM_STU_NUMOF == 6)
- TIMF,
+ TIMF = LL_HRTIM_TIMER_F,
#endif
- MSTR
+ MSTR = LL_HRTIM_TIMER_MASTER
} hrtim_tu_t;
@@ -80,9 +83,13 @@ void hrtim_pwm_set(hrtim_t dev, hrtim_tu_t tu, uint16_t value, uint16_t shift);
void hrtim_init_current();
void hrtim_init_voltage_buck();
+void hrtim_init_voltage_buck_center_aligned();
void hrtim_init_voltage_boost();
+void hrtim_init_voltage_boost_center_aligned();
void hrtim_init_voltage_leg1_buck_leg2_boost();
+void hrtim_init_voltage_leg1_buck_leg2_boost_center_aligned();
void hrtim_init_voltage_leg1_boost_leg2_buck();
+void hrtim_init_voltage_leg1_boost_leg2_buck_center_aligned();
void hrtim_update_adc_trig_interleaved(uint16_t new_trig);
diff --git a/zephyr/modules/owntech_hrtim_driver/zephyr/public_include/leg.h b/zephyr/modules/owntech_hrtim_driver/zephyr/public_include/leg.h
index efa480e..71bcdd1 100644
--- a/zephyr/modules/owntech_hrtim_driver/zephyr/public_include/leg.h
+++ b/zephyr/modules/owntech_hrtim_driver/zephyr/public_include/leg.h
@@ -29,6 +29,7 @@
* @author Hugues Larrive <hugues.larrive@laas.fr>
* @author Antoine Boche <antoine.boche@laas.fr>
* @author Luiz Villa <luiz.villa@laas.fr>
+ * @author Ayoub Farah Hassan <ayoub.farah-hassan@laas.fr>
*/
#ifndef LEG_H_
@@ -68,6 +69,16 @@ typedef struct {
*/
uint16_t leg_init(bool leg1_upper_switch_convention, bool leg2_upper_switch_convention);
+/**
+ * @brief Initializes all the configured devices with up-down mode and the chosen switch convention
+ *
+ * @param[in] leg1_upper_switch_convention Choice of the switch convention for leg 1
+ * @param[in] leg2_upper_switch_convention Choice of the switch convention for leg 2
+ *
+ * @return HRTIM period
+ */
+uint16_t leg_init_center_aligned(bool leg1_upper_switch_convention, bool leg2_upper_switch_convention);
+
/**
* @brief Set the PWM pulse width for a given leg device
*
diff --git a/zephyr/modules/owntech_hrtim_driver/zephyr/src/hrtim_common.c b/zephyr/modules/owntech_hrtim_driver/zephyr/src/hrtim_common.c
index 2f6ac9c..74fd7ad 100644
--- a/zephyr/modules/owntech_hrtim_driver/zephyr/src/hrtim_common.c
+++ b/zephyr/modules/owntech_hrtim_driver/zephyr/src/hrtim_common.c
@@ -22,6 +22,7 @@
*
* @author Clément Foucher <clement.foucher@laas.fr>
* @author Luiz Villa <luiz.villa@laas.fr>
+ * @author Ayoub Farah Hassan <ayoub.farah-hassan@laas.fr>
*/
#include <stm32_ll_hrtim.h>
@@ -38,6 +39,18 @@ void _hrtim_init_events()
hrtim_update_adc_trig_interleaved(1);
}
+void _hrtim_init_events_center_aligned()
+{
+
+ // setting the adc roll-over mode on period event
+ LL_HRTIM_TIM_SetADCRollOverMode(HRTIM1, LL_HRTIM_TIMER_A, LL_HRTIM_ROLLOVER_MODE_PER);
+ LL_HRTIM_TIM_SetADCRollOverMode(HRTIM1, LL_HRTIM_TIMER_B, LL_HRTIM_ROLLOVER_MODE_PER);
+
+ // setting adc trigger
+ hrtim_adc_trigger_en(1, 1, LL_HRTIM_ADCTRIG_SRC13_TIMAPER);
+ hrtim_adc_trigger_en(3, 2, LL_HRTIM_ADCTRIG_SRC13_TIMBPER);
+}
+
void hrtim_update_adc_trig_interleaved(uint16_t new_trig)
{
hrtim_cmp_set(0, TIMA, CMP3xR, new_trig);
@@ -58,20 +71,44 @@ void hrtim_init_voltage_buck()
_hrtim_init_events();
}
+void hrtim_init_voltage_buck_center_aligned()
+{
+ leg_init_center_aligned(true,true);
+ _hrtim_init_events_center_aligned();
+}
+
void hrtim_init_voltage_boost()
{
leg_init(false,false);
_hrtim_init_events();
}
+void hrtim_init_voltage_boost_center_aligned()
+{
+ leg_init_center_aligned(false,false);
+ _hrtim_init_events_center_aligned();
+}
+
void hrtim_init_voltage_leg1_buck_leg2_boost()
{
leg_init(true,false);
_hrtim_init_events();
}
+void hrtim_init_voltage_leg1_buck_leg2_boost_center_aligned()
+{
+ leg_init_center_aligned(true,false);
+ _hrtim_init_events_center_aligned();
+}
+
void hrtim_init_voltage_leg1_boost_leg2_buck()
{
leg_init(false,true);
_hrtim_init_events();
}
+
+void hrtim_init_voltage_leg1_boost_leg2_buck_center_aligned()
+{
+ leg_init_center_aligned(false,true);
+ _hrtim_init_events_center_aligned();
+}
diff --git a/zephyr/modules/owntech_hrtim_driver/zephyr/src/voltage_mode/hrtim_voltage_mode.c b/zephyr/modules/owntech_hrtim_driver/zephyr/src/voltage_mode/hrtim_voltage_mode.c
index b3b7b0b..e54cd5c 100644
--- a/zephyr/modules/owntech_hrtim_driver/zephyr/src/voltage_mode/hrtim_voltage_mode.c
+++ b/zephyr/modules/owntech_hrtim_driver/zephyr/src/voltage_mode/hrtim_voltage_mode.c
@@ -30,29 +30,55 @@
* @author Clément Foucher <clement.foucher@laas.fr>
* @author Antoine Boche <antoine.boche@laas.fr>
* @author Luiz Villa <luiz.villa@laas.fr>
+ * @author Ayoub Farah Hassan <ayoub.farah-hassan@laas.fr>
*/
#include <stm32_ll_rcc.h>
-#include <stm32_ll_hrtim.h>
+#include <stm32_ll_bus.h>
+
#include "hrtim_voltage_mode.h"
#include "assert.h"
+
static const struct soc_gpio_pinctrl tim_pinctrl[] = ST_STM32_DT_INST_PINCTRL(0, 0);
-static inline HRTIM_TypeDef *dev(hrtim_t hrtim)
+static uint8_t _TU_num1(hrtim_tu_t tu) /* Return the number associated to the timing unit */
{
- return HRTIM1;
+
+ switch(tu){
+ case TIMA:
+ return 0;
+
+ case TIMB:
+ return 1;
+
+ case TIMC:
+ return 2;
+
+ case TIMD:
+ return 3;
+
+ case TIME:
+ return 4;
+ #if (HRTIM_STU_NUMOF == 6)
+ case TIMF:
+ return 5;
+ #endif
+ default:
+ return 100;
+
+ }
}
static inline void _clk_init(hrtim_t hrtim)
{
-#if defined(CPU_FAM_STM32F3) || defined(CONFIG_SOC_SERIES_STM32F3X)
+ #if defined(CPU_FAM_STM32F3) || defined(CONFIG_SOC_SERIES_STM32F3X)
/* 1. selection of the high-speed PLL output */
RCC->CFGR3 |= hrtim_config[hrtim].rcc_sw_mask;
-#endif
+ #endif
/* 2. clock enable for the registers mapped on the APB2 bus */
- RCC->APB2ENR |= RCC_APB2ENR_HRTIM1EN;
+ LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_HRTIM1);
__DSB(); // from cmsis_armcc.h
/* Data Synchronization Barrier
@@ -63,29 +89,32 @@ static inline void _clk_init(hrtim_t hrtim)
/* HRTIM DLL initialization */
/* DLL calibration: periodic calibration enabled, period set to 14μs */
- dev(hrtim)->sCommonRegs.DLLCR = HRTIM_DLLCR_CALRTE_1
- | HRTIM_DLLCR_CALRTE_0
- | HRTIM_DLLCR_CALEN;
+ LL_HRTIM_ConfigDLLCalibration(HRTIM1, LL_HRTIM_DLLCALIBRATION_MODE_CONTINUOUS, LL_HRTIM_DLLCALIBRATION_RATE_3);
/* Check DLL end of calibration flag */
- while(!(dev(hrtim)->sCommonRegs.ISR & HRTIM_IER_DLLRDY)) {}
+ while(LL_HRTIM_IsActiveFlag_DLLRDY(HRTIM1) == RESET)
+ {
+ // Wait
+ }
}
static inline unsigned _msb(unsigned v)
-{
+{
+ /* Return the most significant bit */
+
return 8 * sizeof(v) - __builtin_clz(v) - 1;
}
static inline uint32_t _period_ckpsc(hrtim_t hrtim, uint32_t freq,
uint16_t *per, uint8_t *ckpsc)
{
-#if defined(CONFIG_SOC_SERIES_STM32F3X)
- uint32_t f_hrtim = hrtim_get_apb2_clock() * 2;
-#elif defined(CONFIG_SOC_SERIES_STM32G4X)
- uint32_t f_hrtim = hrtim_get_apb2_clock();
-#else
-#warning "unsupported stm32XX family"
-#endif
+ #if defined(CONFIG_SOC_SERIES_STM32F3X)
+ uint32_t f_hrtim = hrtim_get_apb2_clock() * 2;
+ #elif defined(CONFIG_SOC_SERIES_STM32G4X)
+ uint32_t f_hrtim = hrtim_get_apb2_clock();
+ #else
+ #warning "unsupported stm32XX family"
+ #endif
/* t_hrck = f_hrck / freq but f_hrck = (f_hrtim * 32) which is too
* big for an uint32 so we will firstly divide f_hrtim then also add
@@ -115,7 +144,7 @@ static inline uint32_t _period_ckpsc(hrtim_t hrtim, uint32_t freq,
}
/* Verify parameters */
assert( (*ckpsc <= 7)
- && (hrtim < HRTIM_NUMOF)
+ && (hrtim < HRTIM_NUMOF)
&& (period >= min_period)
&& (period <= max_period));
@@ -139,115 +168,142 @@ uint16_t hrtim_init(hrtim_t hrtim, uint32_t *freq, uint16_t dt, uint8_t leg1_upp
/* Master timer initialization */
uint16_t period = hrtim_init_master(hrtim, freq);
- /* Slave timers initialization */
- for (unsigned tu = 0; tu < HRTIM_STU_NUMOF; tu++) {
- hrtim_init_tu(hrtim, tu, freq);
+ /* Timer A initialization for leg 1 */
+ hrtim_init_tu(hrtim, TIMA, freq, Lft_aligned);
+ hrtim_pwm_dt(hrtim, TIMA, dt); // Set the dead time. Note: this must be done before enable counter
+ hrtim_cnt_en(hrtim, TIMA); // Enable counter
+ hrtim_rst_evt_en(hrtim, TIMA, LL_HRTIM_RESETTRIG_MASTER_PER); // We synchronize the Timer A with the master timer, with a reset on period event
- /* Set the dead time
- * Note: this must be done before enable counter */
- hrtim_pwm_dt(hrtim, tu, dt);
+ /* Timer B initialization for leg 2 */
+ hrtim_init_tu(hrtim, TIMB, freq, Lft_aligned);
+ hrtim_pwm_dt(hrtim, TIMB, dt); // Set the dead time. Note: this must be done before enable counter
+ hrtim_cnt_en(hrtim, TIMB); // Enable the counter
+ hrtim_rst_evt_en(hrtim, TIMB, LL_HRTIM_RESETTRIG_MASTER_PER); // We synchronize the Timer B with the master timer, with a reset on period event
- /* Enable counter */
- hrtim_cnt_en(hrtim, (1 << (HRTIM_MCR_TACEN_Pos + tu)));
- /* Setup outputs */
- hrtim_cmpl_pwm_out1(hrtim, tu, leg1_upper_switch_convention);
- hrtim_cmpl_pwm_out2(hrtim, tu, leg2_upper_switch_convention);
-
- /* Reset on master timer period event */
- hrtim_rst_evt_en(hrtim, tu, RST_MSTPER);
- }
+ hrtim_cmpl_pwm_out1(hrtim, TIMA, leg1_upper_switch_convention, Lft_aligned); // Set the convention for leg 1
+ hrtim_cmpl_pwm_out1(hrtim, TIMB, leg2_upper_switch_convention, Lft_aligned); // Set the convention for leg 2
return period;
}
+uint16_t hrtim_init_updwn(hrtim_t hrtim, uint32_t *freq, uint16_t dt, uint8_t leg1_upper_switch_convention, uint8_t leg2_upper_switch_convention)
+{
+ /* Master timer and timing unit frequency initialization */
+ uint16_t period = hrtim_init_master(hrtim, freq);
+ uint32_t freq_tu = (*freq)*2;
+
+ /* Timer A initialization for leg 1 */
+ hrtim_init_tu(hrtim, TIMA, &freq_tu, UpDwn);
+ hrtim_pwm_dt(hrtim, TIMA, dt); // Set the dead time. Note: this must be done before enable counter
+ hrtim_cnt_en(hrtim, TIMA); // Enable counter
+ hrtim_rst_evt_en(hrtim, TIMA, LL_HRTIM_RESETTRIG_MASTER_PER); // We synchronize the Timer A with the master timer, with a reset on period event
+
+ /* Timer B initialization for leg 2 */
+ hrtim_init_tu(hrtim, TIMB, &freq_tu, UpDwn);
+ hrtim_pwm_dt(hrtim, TIMB, dt); // Set the dead time. Note: this must be done before enable counter
+ hrtim_cnt_en(hrtim, TIMB); // Enable the counter
+ hrtim_rst_evt_en(hrtim, TIMB, LL_HRTIM_RESETTRIG_MASTER_PER); // We synchronize the Timer B with the master timer, with a reset on period event
+
+
+ hrtim_cmpl_pwm_out1(hrtim, TIMA, leg1_upper_switch_convention, UpDwn); // Set the convention for leg 1
+ hrtim_cmpl_pwm_out1(hrtim, TIMB, leg2_upper_switch_convention, UpDwn); // Set the convention for leg 2
+
+ return period/2; // return timing unit period which is half the period of the master timer
+}
+
void hrtim_pwm_set(hrtim_t hrtim, hrtim_tu_t tu, uint16_t value, uint16_t shift)
{
static uint16_t prev_value[HRTIM_STU_NUMOF];
static uint16_t prev_shift[HRTIM_STU_NUMOF];
- if (value != prev_value[tu]) {
- prev_value[tu] = value;
+ uint8_t tu_n = _TU_num1(tu); // timing unit number
+
+ if (value != prev_value[tu_n]) {
+ prev_value[tu_n] = value;
/* Disable outputs when duty cycle is 0 */
if (value == 0) {
- dev(hrtim)->sCommonRegs.ODISR |= ((OUT1 | OUT2) << (tu * 2));
+ hrtim_out_dis(hrtim, tu, OUT1);
+ hrtim_out_dis(hrtim, tu, OUT2);
return;
}
/* Set comparator for duty cycle */
- dev(hrtim)->sTimerxRegs[tu].CMP1xR = value;
+ LL_HRTIM_TIM_SetCompare1(HRTIM1, tu, value);
/* Enable outputs */
- dev(hrtim)->sCommonRegs.OENR |= ((OUT1 | OUT2) << (tu * 2));
+ hrtim_out_en(hrtim, tu, OUT1);
+ hrtim_out_en(hrtim, tu, OUT2);
}
- if (shift != prev_shift[tu]) {
- prev_shift[tu] = shift;
+
+ if (shift != prev_shift[tu_n]) {
+ prev_shift[tu_n] = shift;
/* Set reset comparator for phase positioning */
if (shift) {
- dev(hrtim)->sTimerxRegs[tu].RSTxR &= ~RST_MSTPER;
+ LL_HRTIM_TIM_SetResetTrig(HRTIM1, tu, LL_HRTIM_TIM_GetResetTrig (HRTIM1, tu) &~ LL_HRTIM_RESETTRIG_MASTER_PER);
switch (tu) {
/* Timer A is the phase shift reference so it can't be phase
* shifted */
case TIMB: /* Timer B reset on master cmp1 */
- dev(hrtim)->sMasterRegs.MCMP1R = shift;
- dev(hrtim)->sTimerxRegs[tu].RSTxR |= RST_MSTCMP1;
+ LL_HRTIM_TIM_SetCompare1(HRTIM1, LL_HRTIM_TIMER_MASTER, shift);
+ LL_HRTIM_TIM_SetResetTrig(HRTIM1, LL_HRTIM_TIMER_B, LL_HRTIM_RESETTRIG_MASTER_CMP1);
break;
case TIMC: /* Timer C reset on master cmp2 */
- dev(hrtim)->sMasterRegs.MCMP2R = shift;
- dev(hrtim)->sTimerxRegs[tu].RSTxR |= RST_MSTCMP2;
+ LL_HRTIM_TIM_SetCompare2(HRTIM1, LL_HRTIM_TIMER_MASTER, shift);
+ LL_HRTIM_TIM_SetResetTrig(HRTIM1, LL_HRTIM_TIMER_C, LL_HRTIM_RESETTRIG_MASTER_CMP2);
break;
case TIMD: /* Timer D reset on master cmp3 */
- dev(hrtim)->sMasterRegs.MCMP3R = shift;
- dev(hrtim)->sTimerxRegs[tu].RSTxR |= RST_MSTCMP3;
+ LL_HRTIM_TIM_SetCompare3(HRTIM1, LL_HRTIM_TIMER_MASTER, shift);
+ LL_HRTIM_TIM_SetResetTrig(HRTIM1, LL_HRTIM_TIMER_D, LL_HRTIM_RESETTRIG_MASTER_CMP3);
break;
case TIME: /* Timer E reset on master cmp4 */
- dev(hrtim)->sMasterRegs.MCMP4R = shift;
- dev(hrtim)->sTimerxRegs[tu].RSTxR |= RST_MSTCMP4;
+ LL_HRTIM_TIM_SetCompare4(HRTIM1, LL_HRTIM_TIMER_MASTER, shift);
+ LL_HRTIM_TIM_SetResetTrig(HRTIM1, LL_HRTIM_TIMER_E, LL_HRTIM_RESETTRIG_MASTER_CMP4);
break;
-#if (HRTIM_STU_NUMOF == 6)
+ #if (HRTIM_STU_NUMOF == 6)
case TIMF: /* Timer F reset on timerA cmp2 */
- dev(hrtim)->sTimerxRegs[0].CMP2xR = shift;
- dev(hrtim)->sTimerxRegs[tu].RSTxR |= RSTF_TACMP2;
+ LL_HRTIM_TIM_SetCompare2(HRTIM1, LL_HRTIM_TIMER_A, shift);
+ LL_HRTIM_TIM_SetResetTrig(HRTIM1, tu, LL_HRTIM_RESETTRIG_OTHER1_CMP2);
break;
-#endif
+ #endif
default:
break;
}
}
- else if(dev(hrtim)->sTimerxRegs[tu].PERxR == dev(hrtim)->sMasterRegs.MPER
- && (dev(hrtim)->sTimerxRegs[tu].TIMxCR & HRTIM_TIMCR_CK_PSC_Msk)
- == (dev(hrtim)->sMasterRegs.MCR & HRTIM_MCR_CK_PSC_Msk)){
+ else if(LL_HRTIM_TIM_GetPeriod(HRTIM1,LL_HRTIM_TIMER_MASTER) == LL_HRTIM_TIM_GetPeriod(HRTIM1, tu)
+ && LL_HRTIM_TIM_GetPrescaler (HRTIM1, LL_HRTIM_TIMER_MASTER) == LL_HRTIM_TIM_GetPrescaler(HRTIM1, tu)){
/* shift == 0 and timing unit run at the same frequency as master */
switch (tu) {
case TIMB:
- dev(hrtim)->sTimerxRegs[tu].RSTxR &= ~RST_MSTCMP1;
+ LL_HRTIM_TIM_SetResetTrig(HRTIM1, LL_HRTIM_TIMER_B, LL_HRTIM_TIM_GetResetTrig (HRTIM1, LL_HRTIM_TIMER_B) &~ LL_HRTIM_RESETTRIG_MASTER_CMP1);
break;
case TIMC:
- dev(hrtim)->sTimerxRegs[tu].RSTxR &= ~RST_MSTCMP2;
+ LL_HRTIM_TIM_SetResetTrig(HRTIM1, LL_HRTIM_TIMER_C, LL_HRTIM_TIM_GetResetTrig (HRTIM1, LL_HRTIM_TIMER_C) &~ LL_HRTIM_RESETTRIG_MASTER_CMP2);
break;
case TIMD:
- dev(hrtim)->sTimerxRegs[tu].RSTxR &= ~RST_MSTCMP3;
+ LL_HRTIM_TIM_SetResetTrig(HRTIM1, LL_HRTIM_TIMER_D, LL_HRTIM_TIM_GetResetTrig (HRTIM1, LL_HRTIM_TIMER_D) &~ LL_HRTIM_RESETTRIG_MASTER_CMP3);
break;
case TIME:
- dev(hrtim)->sTimerxRegs[tu].RSTxR &= ~RST_MSTCMP4;
+ LL_HRTIM_TIM_SetResetTrig(HRTIM1, LL_HRTIM_TIMER_E, LL_HRTIM_TIM_GetResetTrig (HRTIM1, LL_HRTIM_TIMER_E) &~ LL_HRTIM_RESETTRIG_MASTER_CMP4);
break;
-#if (HRTIM_STU_NUMOF == 6)
+ #if (HRTIM_STU_NUMOF == 6)
case TIMF:
- dev(hrtim)->sTimerxRegs[tu].RSTxR &= ~RSTF_TACMP2;
+ LL_HRTIM_TIM_SetResetTrig(HRTIM1, LL_HRTIM_TIMER_F, LL_HRTIM_TIM_GetResetTrig (HRTIM1, LL_HRTIM_TIMER_F) &~ LL_HRTIM_RESETTRIG_OTHER1_CMP2);
break;
-#endif
+ #endif
default:
break;
}
- dev(hrtim)->sTimerxRegs[tu].RSTxR |= RST_MSTPER;
+ LL_HRTIM_TIM_SetResetTrig(HRTIM1, tu, LL_HRTIM_RESETTRIG_MASTER_PER);
}
else {
/* timing unit do not run at the same frequency as master so
* phase positioning is not applicable */
- dev(hrtim)->sTimerxRegs[tu].RSTxR &= ~RST_MSTPER;
- }
- }
+ LL_HRTIM_TIM_SetResetTrig(HRTIM1, tu, LL_HRTIM_TIM_GetResetTrig (HRTIM1, tu) &~ LL_HRTIM_RESETTRIG_MASTER_PER);
+ }
+ }
+
}
uint16_t hrtim_init_master(hrtim_t hrtim, uint32_t *freq)
@@ -262,157 +318,257 @@ uint16_t hrtim_init_master(hrtim_t hrtim, uint32_t *freq)
* bitfields before writing the compare and period registers. */
*freq = _period_ckpsc(hrtim, *freq, &period, &ckpsc);
/* master timer prescaler init */
- dev(hrtim)->sMasterRegs.MCR &= ~HRTIM_MCR_CK_PSC_Msk;
- dev(hrtim)->sMasterRegs.MCR |= (ckpsc << HRTIM_MCR_CK_PSC_Pos);
+ LL_HRTIM_TIM_SetPrescaler(HRTIM1, LL_HRTIM_TIMER_MASTER, ckpsc);
/* Master timer initialization */
/* continuous mode, preload enabled on repetition event */
- dev(hrtim)->sMasterRegs.MCR |= (HRTIM_MCR_CONT | HRTIM_MCR_PREEN
- | HRTIM_MCR_MREPU);
+
+ LL_HRTIM_TIM_SetCounterMode(HRTIM1,LL_HRTIM_TIMER_MASTER, LL_HRTIM_MODE_CONTINUOUS);
+ LL_HRTIM_TIM_EnablePreload(HRTIM1, LL_HRTIM_TIMER_MASTER);
+ LL_HRTIM_TIM_SetUpdateTrig(HRTIM1, LL_HRTIM_TIMER_MASTER, LL_HRTIM_UPDATETRIG_REPETITION);
/* Enable counter */
- dev(hrtim)->sMasterRegs.MCR |= (1 << HRTIM_MCR_MCEN_Pos);
+ LL_HRTIM_TIM_CounterEnable(HRTIM1, LL_HRTIM_TIMER_MASTER);
/* Configure the PWM frequency by setting the period registers */
- dev(hrtim)->sMasterRegs.MPER = period;
+ LL_HRTIM_TIM_SetPeriod(HRTIM1, LL_HRTIM_TIMER_MASTER, period);
return period;
}
-uint16_t hrtim_init_tu(hrtim_t hrtim, hrtim_tu_t tu, uint32_t *freq)
+uint16_t hrtim_init_tu(hrtim_t hrtim, hrtim_tu_t tu, uint32_t *freq, hrtim_cnt_t cnt_mode)
{
uint16_t period;
uint8_t ckpsc;
/* Outputs initialization */
- hrtim_out_dis(hrtim, tu, OUT1 | OUT2);
+
+ hrtim_out_dis(hrtim, tu, OUT1);
+ hrtim_out_dis(hrtim, tu, OUT2);
+
stm32_dt_pinctrl_configure(tim_pinctrl, ARRAY_SIZE(tim_pinctrl), HRTIM1_BASE);
/* At start-up, it is mandatory to initialize first the prescaler
* bitfields before writing the compare and period registers. */
+
*freq = _period_ckpsc(hrtim, *freq, &period, &ckpsc);
- dev(hrtim)->sTimerxRegs[tu].TIMxCR &= ~HRTIM_TIMCR_CK_PSC_Msk;
- dev(hrtim)->sTimerxRegs[tu].TIMxCR |= (ckpsc << HRTIM_TIMCR_CK_PSC_Pos);
+ LL_HRTIM_TIM_SetPrescaler(HRTIM1, tu, ckpsc);
/* timer initialization */
/* continuous mode, preload enabled on repetition event */
- dev(hrtim)->sTimerxRegs[tu].TIMxCR |= (HRTIM_TIMCR_CONT
- | HRTIM_TIMCR_PREEN
- | HRTIM_TIMCR_TREPU);
+
+ LL_HRTIM_TIM_SetCounterMode(HRTIM1, tu, LL_HRTIM_MODE_CONTINUOUS);
+ LL_HRTIM_TIM_EnablePreload(HRTIM1, tu);
+ LL_HRTIM_TIM_SetUpdateTrig(HRTIM1, tu, LL_HRTIM_UPDATETRIG_REPETITION);
+
+ /* Set the counting mode, left aligned or up-down (center aligned) */
- /* Configure the PWM frequency by setting the period registers */
- dev(hrtim)->sTimerxRegs[tu].PERxR = period;
+ if(cnt_mode == UpDwn){LL_HRTIM_TIM_SetCountingMode(HRTIM1, tu, LL_HRTIM_COUNTING_MODE_UP_DOWN);}
+ /* Configure the PWM frequency by setting the period registers */
+ LL_HRTIM_TIM_SetPeriod(HRTIM1, tu, period);
return period;
}
-void hrtim_set_cb_set(hrtim_t hrtim, hrtim_tu_t tu, hrtim_out_t out,
- hrtim_cb_t cb)
+void hrtim_set_cb_set(hrtim_t hrtim, uint32_t out,
+ uint32_t cb)
{
- if (out == OUT1) {
- dev(hrtim)->sTimerxRegs[tu].SETx1R |= cb;
- }
- else { /* OUT2 */
- dev(hrtim)->sTimerxRegs[tu].SETx2R |= cb;
- }
+ LL_HRTIM_OUT_SetOutputSetSrc(HRTIM1, out, cb);
}
-void hrtim_set_cb_unset(hrtim_t hrtim, hrtim_tu_t tu, hrtim_out_t out,
- hrtim_cb_t cb)
+void hrtim_set_cb_unset(hrtim_t hrtim, uint32_t out,
+ uint32_t cb)
{
- if (out == OUT1) {
- dev(hrtim)->sTimerxRegs[tu].SETx1R &= ~cb;
- }
- else { /* OUT2 */
- dev(hrtim)->sTimerxRegs[tu].SETx2R &= ~cb;
- }
+ LL_HRTIM_OUT_SetOutputSetSrc(HRTIM1, out, LL_HRTIM_OUT_GetOutputSetSrc(HRTIM1, out) & ~cb );
}
-void hrtim_rst_cb_set(hrtim_t hrtim, hrtim_tu_t tu, hrtim_out_t out,
- hrtim_cb_t cb)
+void hrtim_rst_cb_set(hrtim_t hrtim, uint32_t out,
+ uint32_t cb)
{
- if (out == OUT1) {
- dev(hrtim)->sTimerxRegs[tu].RSTx1R |= cb;
- }
- else { /* OUT2 */
- dev(hrtim)->sTimerxRegs[tu].RSTx2R |= cb;
- }
+ LL_HRTIM_OUT_SetOutputResetSrc(HRTIM1, out, cb);
}
-void hrtim_rst_cb_unset(hrtim_t hrtim, hrtim_tu_t tu, hrtim_out_t out,
- hrtim_cb_t cb)
+void hrtim_rst_cb_unset(hrtim_t hrtim, uint32_t out,
+ uint32_t cb)
{
- if (out == OUT1) {
- dev(hrtim)->sTimerxRegs[tu].RSTx1R &= ~cb;
- }
- else { /* OUT2 */
- dev(hrtim)->sTimerxRegs[tu].RSTx2R &= ~cb;
- }
+ LL_HRTIM_OUT_SetOutputResetSrc(HRTIM1, out, LL_HRTIM_OUT_GetOutputResetSrc(HRTIM1,out) & ~cb );
}
-void hrtim_cmpl_pwm_out(hrtim_t hrtim, hrtim_tu_t tu, bool upper_switch_convention)
+
+void hrtim_cmpl_pwm_out1(hrtim_t hrtim, hrtim_tu_t tu, bool leg_upper_switch_convention, hrtim_cnt_t cnt_mode)
{
- // Configuration for the upper switch convention
- if (upper_switch_convention == true)
- {
- dev(hrtim)->sTimerxRegs[tu].SETx1R = PER;
- dev(hrtim)->sTimerxRegs[tu].RSTx1R = CMP1;
- dev(hrtim)->sTimerxRegs[tu].SETx2R = CMP1;
- dev(hrtim)->sTimerxRegs[tu].RSTx2R = PER;
- }
+ // Configuration for the upper switch convention in buck mode
+ if (leg_upper_switch_convention == true)
+ { switch(tu){
+
+ case TIMA:
+ if(cnt_mode == Lft_aligned){LL_HRTIM_OUT_SetOutputSetSrc(HRTIM1, LL_HRTIM_OUTPUT_TA1, LL_HRTIM_OUTPUTSET_TIMPER);}
+ LL_HRTIM_OUT_SetOutputResetSrc(HRTIM1, LL_HRTIM_OUTPUT_TA1, LL_HRTIM_OUTPUTRESET_TIMCMP1);
+ break;
+
+ case TIMB:
+ if(cnt_mode == Lft_aligned){LL_HRTIM_OUT_SetOutputSetSrc(HRTIM1, LL_HRTIM_OUTPUT_TB1, LL_HRTIM_OUTPUTSET_TIMPER);}
+ LL_HRTIM_OUT_SetOutputResetSrc(HRTIM1, LL_HRTIM_OUTPUT_TB1, LL_HRTIM_OUTPUTRESET_TIMCMP1);
+ break;
+
+ case TIMC:
+ if(cnt_mode == Lft_aligned){LL_HRTIM_OUT_SetOutputSetSrc(HRTIM1, LL_HRTIM_OUTPUT_TC1, LL_HRTIM_OUTPUTSET_TIMPER);}
+ LL_HRTIM_OUT_SetOutputResetSrc(HRTIM1, LL_HRTIM_OUTPUT_TC1, LL_HRTIM_OUTPUTRESET_TIMCMP1);
+ break;
+
+ case TIMD:
+ if(cnt_mode == Lft_aligned){LL_HRTIM_OUT_SetOutputSetSrc(HRTIM1, LL_HRTIM_OUTPUT_TD1, LL_HRTIM_OUTPUTSET_TIMPER);}
+ LL_HRTIM_OUT_SetOutputResetSrc(HRTIM1, LL_HRTIM_OUTPUT_TD1, LL_HRTIM_OUTPUTRESET_TIMCMP1);
+ break;
+
+ case TIME:
+ if(cnt_mode == Lft_aligned){LL_HRTIM_OUT_SetOutputSetSrc(HRTIM1, LL_HRTIM_OUTPUT_TE1, LL_HRTIM_OUTPUTSET_TIMPER);}
+ LL_HRTIM_OUT_SetOutputResetSrc(HRTIM1, LL_HRTIM_OUTPUT_TE1, LL_HRTIM_OUTPUTRESET_TIMCMP1);
+ break;
+
+ case TIMF:
+ if(cnt_mode == Lft_aligned){LL_HRTIM_OUT_SetOutputSetSrc(HRTIM1, LL_HRTIM_OUTPUT_TF1, LL_HRTIM_OUTPUTSET_TIMPER);}
+ LL_HRTIM_OUT_SetOutputResetSrc(HRTIM1, LL_HRTIM_OUTPUT_TF1, LL_HRTIM_OUTPUTRESET_TIMCMP1);
+ break;
+
+ default:
+ break;
- // Configuration for the lower switch convention
- else if (upper_switch_convention == false)
- {
- dev(hrtim)->sTimerxRegs[tu].SETx1R = CMP1;
- dev(hrtim)->sTimerxRegs[tu].RSTx1R = PER;
- dev(hrtim)->sTimerxRegs[tu].SETx2R = PER;
- dev(hrtim)->sTimerxRegs[tu].RSTx2R = CMP1;
}
-}
-
-void hrtim_cmpl_pwm_out1(hrtim_t hrtim, hrtim_tu_t tu, bool leg1_upper_switch_convention)
-{
- // Configuration for the upper switch convention
- if (leg1_upper_switch_convention == true)
- {
- dev(hrtim)->sTimerxRegs[tu].SETx1R = PER;
- dev(hrtim)->sTimerxRegs[tu].RSTx1R = CMP1;
}
- // Configuration for the lower switch convention
- else if (leg1_upper_switch_convention == false)
+ // Configuration for the upper switch convention in boost mode
+ else if (leg_upper_switch_convention == false)
{
- dev(hrtim)->sTimerxRegs[tu].SETx1R = CMP1;
- dev(hrtim)->sTimerxRegs[tu].RSTx1R = PER;
+ switch(tu){
+
+ case TIMA:
+ LL_HRTIM_OUT_SetOutputSetSrc(HRTIM1, LL_HRTIM_OUTPUT_TA1, LL_HRTIM_OUTPUTSET_TIMCMP1);
+ if(cnt_mode == Lft_aligned){LL_HRTIM_OUT_SetOutputResetSrc(HRTIM1, LL_HRTIM_OUTPUT_TA1, LL_HRTIM_OUTPUTRESET_TIMPER);}
+ break;
+
+ case TIMB:
+ LL_HRTIM_OUT_SetOutputSetSrc(HRTIM1, LL_HRTIM_OUTPUT_TB1, LL_HRTIM_OUTPUTSET_TIMCMP1);
+ if(cnt_mode == Lft_aligned){LL_HRTIM_OUT_SetOutputResetSrc(HRTIM1, LL_HRTIM_OUTPUT_TB1, LL_HRTIM_OUTPUTRESET_TIMPER);}
+ break;
+
+ case TIMC:
+ LL_HRTIM_OUT_SetOutputSetSrc(HRTIM1, LL_HRTIM_OUTPUT_TC1, LL_HRTIM_OUTPUTSET_TIMCMP1);
+ if(cnt_mode == Lft_aligned){LL_HRTIM_OUT_SetOutputResetSrc(HRTIM1, LL_HRTIM_OUTPUT_TC1, LL_HRTIM_OUTPUTRESET_TIMPER);}
+ break;
+
+ case TIMD:
+ LL_HRTIM_OUT_SetOutputSetSrc(HRTIM1, LL_HRTIM_OUTPUT_TD1, LL_HRTIM_OUTPUTSET_TIMCMP1);
+ if(cnt_mode == Lft_aligned){LL_HRTIM_OUT_SetOutputResetSrc(HRTIM1, LL_HRTIM_OUTPUT_TD1, LL_HRTIM_OUTPUTRESET_TIMPER);}
+ break;
+
+ case TIME:
+ LL_HRTIM_OUT_SetOutputSetSrc(HRTIM1, LL_HRTIM_OUTPUT_TE1, LL_HRTIM_OUTPUTSET_TIMCMP1);
+ if(cnt_mode == Lft_aligned){LL_HRTIM_OUT_SetOutputResetSrc(HRTIM1, LL_HRTIM_OUTPUT_TE1, LL_HRTIM_OUTPUTRESET_TIMPER);}
+ break;
+
+ case TIMF:
+ LL_HRTIM_OUT_SetOutputSetSrc(HRTIM1, LL_HRTIM_OUTPUT_TF1, LL_HRTIM_OUTPUTSET_TIMCMP1);
+ if(cnt_mode == Lft_aligned){LL_HRTIM_OUT_SetOutputResetSrc(HRTIM1, LL_HRTIM_OUTPUT_TF1, LL_HRTIM_OUTPUTRESET_TIMPER);}
+ break;
+
+ default:
+ break;
+
+ }
}
}
-void hrtim_cmpl_pwm_out2(hrtim_t hrtim, hrtim_tu_t tu, bool leg2_upper_switch_convention)
+
+void hrtim_cmpl_pwm_out2(hrtim_t hrtim, hrtim_tu_t tu, bool leg_lower_switch_convention, hrtim_cnt_t cnt_mode)
{
- // Configuration for the upper switch convention
- if (leg2_upper_switch_convention == true)
- {
- dev(hrtim)->sTimerxRegs[tu].SETx2R = CMP1;
- dev(hrtim)->sTimerxRegs[tu].RSTx2R = PER;
+ // Configuration for the lower switch convention in buck mode
+ if (leg_lower_switch_convention == true)
+ {
+ switch(tu){
+
+ case TIMA:
+ LL_HRTIM_OUT_SetOutputSetSrc(HRTIM1, LL_HRTIM_OUTPUT_TA2, LL_HRTIM_OUTPUTSET_TIMCMP1);
+ if(cnt_mode == Lft_aligned){LL_HRTIM_OUT_SetOutputResetSrc(HRTIM1, LL_HRTIM_OUTPUT_TA2, LL_HRTIM_OUTPUTRESET_TIMPER);}
+ break;
+
+ case TIMB:
+ LL_HRTIM_OUT_SetOutputSetSrc(HRTIM1, LL_HRTIM_OUTPUT_TB2, LL_HRTIM_OUTPUTSET_TIMCMP1);
+ if(cnt_mode == Lft_aligned){LL_HRTIM_OUT_SetOutputResetSrc(HRTIM1, LL_HRTIM_OUTPUT_TB2, LL_HRTIM_OUTPUTRESET_TIMPER);}
+ break;
+
+ case TIMC:
+ LL_HRTIM_OUT_SetOutputSetSrc(HRTIM1, LL_HRTIM_OUTPUT_TC2, LL_HRTIM_OUTPUTSET_TIMCMP1);
+ if(cnt_mode == Lft_aligned){LL_HRTIM_OUT_SetOutputResetSrc(HRTIM1, LL_HRTIM_OUTPUT_TC2, LL_HRTIM_OUTPUTRESET_TIMPER);}
+ break;
+
+ case TIMD:
+ LL_HRTIM_OUT_SetOutputSetSrc(HRTIM1, LL_HRTIM_OUTPUT_TD2, LL_HRTIM_OUTPUTSET_TIMCMP1);
+ if(cnt_mode == Lft_aligned){LL_HRTIM_OUT_SetOutputResetSrc(HRTIM1, LL_HRTIM_OUTPUT_TD2, LL_HRTIM_OUTPUTRESET_TIMPER);}
+ break;
+
+ case TIME:
+ LL_HRTIM_OUT_SetOutputSetSrc(HRTIM1, LL_HRTIM_OUTPUT_TE2, LL_HRTIM_OUTPUTSET_TIMCMP1);
+ if(cnt_mode == Lft_aligned){LL_HRTIM_OUT_SetOutputResetSrc(HRTIM1, LL_HRTIM_OUTPUT_TE2, LL_HRTIM_OUTPUTRESET_TIMPER);}
+ break;
+
+ case TIMF:
+ LL_HRTIM_OUT_SetOutputSetSrc(HRTIM1, LL_HRTIM_OUTPUT_TF2, LL_HRTIM_OUTPUTSET_TIMCMP1);
+ if(cnt_mode == Lft_aligned){LL_HRTIM_OUT_SetOutputResetSrc(HRTIM1, LL_HRTIM_OUTPUT_TF2, LL_HRTIM_OUTPUTRESET_TIMPER);}
+ break;
+
+ default:
+ break;
+
+ }
}
- // Configuration for the lower switch convention
- else if (leg2_upper_switch_convention == false)
- {
- dev(hrtim)->sTimerxRegs[tu].SETx2R = PER;
- dev(hrtim)->sTimerxRegs[tu].RSTx2R = CMP1;
+ // Configuration for the lower switch convention in boost mode
+ else if (leg_lower_switch_convention == false)
+ {
+ switch(tu){
+
+ case TIMA:
+ if(cnt_mode == Lft_aligned){LL_HRTIM_OUT_SetOutputSetSrc(HRTIM1, LL_HRTIM_OUTPUT_TA2, LL_HRTIM_OUTPUTSET_TIMPER);}
+ LL_HRTIM_OUT_SetOutputResetSrc(HRTIM1, LL_HRTIM_OUTPUT_TA2, LL_HRTIM_OUTPUTRESET_TIMCMP1);
+ break;
+
+ case TIMB:
+ if(cnt_mode == Lft_aligned){LL_HRTIM_OUT_SetOutputSetSrc(HRTIM1, LL_HRTIM_OUTPUT_TB2, LL_HRTIM_OUTPUTSET_TIMPER);}
+ LL_HRTIM_OUT_SetOutputResetSrc(HRTIM1, LL_HRTIM_OUTPUT_TB2, LL_HRTIM_OUTPUTRESET_TIMCMP1);
+ break;
+
+ case TIMC:
+ if(cnt_mode == Lft_aligned){LL_HRTIM_OUT_SetOutputSetSrc(HRTIM1, LL_HRTIM_OUTPUT_TC2, LL_HRTIM_OUTPUTSET_TIMPER);}
+ LL_HRTIM_OUT_SetOutputResetSrc(HRTIM1, LL_HRTIM_OUTPUT_TC2, LL_HRTIM_OUTPUTRESET_TIMCMP1);
+ break;
+
+ case TIMD:
+ if(cnt_mode == Lft_aligned){LL_HRTIM_OUT_SetOutputSetSrc(HRTIM1, LL_HRTIM_OUTPUT_TD2, LL_HRTIM_OUTPUTSET_TIMPER);}
+ LL_HRTIM_OUT_SetOutputResetSrc(HRTIM1, LL_HRTIM_OUTPUT_TD2, LL_HRTIM_OUTPUTRESET_TIMCMP1);
+ break;
+
+ case TIME:
+ if(cnt_mode == Lft_aligned){LL_HRTIM_OUT_SetOutputSetSrc(HRTIM1, LL_HRTIM_OUTPUT_TE2, LL_HRTIM_OUTPUTSET_TIMPER);}
+ LL_HRTIM_OUT_SetOutputResetSrc(HRTIM1, LL_HRTIM_OUTPUT_TE2, LL_HRTIM_OUTPUTRESET_TIMCMP1);
+ break;
+
+ case TIMF:
+ if(cnt_mode == Lft_aligned){LL_HRTIM_OUT_SetOutputSetSrc(HRTIM1, LL_HRTIM_OUTPUT_TF2, LL_HRTIM_OUTPUTSET_TIMPER);}
+ LL_HRTIM_OUT_SetOutputResetSrc(HRTIM1, LL_HRTIM_OUTPUT_TF2, LL_HRTIM_OUTPUTRESET_TIMCMP1);
+ break;
+
+ default:
+ break;
+
+ }
}
}
+
void hrtim_period_set(hrtim_t hrtim, hrtim_tu_t tu, uint16_t value)
{
- if (tu == MSTR) {
- dev(hrtim)->sMasterRegs.MPER = value;
- }
- else {
- dev(hrtim)->sTimerxRegs[tu].PERxR = value;
- }
+ LL_HRTIM_TIM_SetPeriod(HRTIM1, tu, value);
}
void hrtim_cmp_set(hrtim_t hrtim, hrtim_tu_t tu, hrtim_cmp_t cmp,
@@ -421,16 +577,16 @@ void hrtim_cmp_set(hrtim_t hrtim, hrtim_tu_t tu, hrtim_cmp_t cmp,
if (tu == MSTR) {
switch (cmp) {
case MCMP1R:
- dev(hrtim)->sMasterRegs.MCMP1R = value;
+ LL_HRTIM_TIM_SetCompare1(HRTIM1,LL_HRTIM_TIMER_MASTER,value);
break;
case MCMP2R:
- dev(hrtim)->sMasterRegs.MCMP2R = value;
+ LL_HRTIM_TIM_SetCompare2(HRTIM1,LL_HRTIM_TIMER_MASTER,value);
break;
case MCMP3R:
- dev(hrtim)->sMasterRegs.MCMP3R = value;
+ LL_HRTIM_TIM_SetCompare3(HRTIM1,LL_HRTIM_TIMER_MASTER,value);
break;
case MCMP4R:
- dev(hrtim)->sMasterRegs.MCMP4R = value;
+ LL_HRTIM_TIM_SetCompare4(HRTIM1, LL_HRTIM_TIMER_MASTER, value);
break;
default:
break;
@@ -439,16 +595,16 @@ void hrtim_cmp_set(hrtim_t hrtim, hrtim_tu_t tu, hrtim_cmp_t cmp,
else {
switch (cmp) {
case CMP1xR:
- dev(hrtim)->sTimerxRegs[tu].CMP1xR = value;
+ LL_HRTIM_TIM_SetCompare1(HRTIM1, tu, value);
break;
case CMP2xR:
- dev(hrtim)->sTimerxRegs[tu].CMP2xR = value;
+ LL_HRTIM_TIM_SetCompare2(HRTIM1, tu, value);
break;
case CMP3xR:
- dev(hrtim)->sTimerxRegs[tu].CMP3xR = value;
+ LL_HRTIM_TIM_SetCompare3(HRTIM1, tu, value);
break;
case CMP4xR:
- dev(hrtim)->sTimerxRegs[tu].CMP4xR = value;
+ LL_HRTIM_TIM_SetCompare4(HRTIM1, tu, value);
break;
default:
break;
@@ -456,34 +612,170 @@ void hrtim_cmp_set(hrtim_t hrtim, hrtim_tu_t tu, hrtim_cmp_t cmp,
}
}
-void hrtim_cnt_en(hrtim_t hrtim, hrtim_cen_t cen)
+void hrtim_cnt_en(hrtim_t hrtim, hrtim_tu_t tu)
{
- dev(hrtim)->sMasterRegs.MCR |= cen;
+ LL_HRTIM_TIM_CounterEnable(HRTIM1, tu);
}
-void hrtim_cnt_dis(hrtim_t hrtim, hrtim_cen_t cen)
+void hrtim_cnt_dis(hrtim_t hrtim, hrtim_tu_t tu)
{
- dev(hrtim)->sMasterRegs.MCR &= ~cen;
+ LL_HRTIM_TIM_CounterDisable(HRTIM1, tu);
}
-void hrtim_rst_evt_en(hrtim_t hrtim, hrtim_tu_t tu, hrtim_rst_evt_t evt)
+void hrtim_rst_evt_en(hrtim_t hrtim, hrtim_tu_t tu, uint32_t evt)
{
- dev(hrtim)->sTimerxRegs[tu].RSTxR |= evt;
+ LL_HRTIM_TIM_SetResetTrig(HRTIM1, tu, evt);
}
-void hrtim_rst_evt_dis(hrtim_t hrtim, hrtim_tu_t tu, hrtim_rst_evt_t evt)
+void hrtim_rst_evt_dis(hrtim_t hrtim, hrtim_tu_t tu, uint32_t evt)
{
- dev(hrtim)->sTimerxRegs[tu].RSTxR &= ~evt;
+ LL_HRTIM_TIM_SetResetTrig(HRTIM1, tu, LL_HRTIM_TIM_GetResetTrig(HRTIM1, tu) &~ evt);
}
void hrtim_out_en(hrtim_t hrtim, hrtim_tu_t tu, hrtim_out_t out)
-{
- dev(hrtim)->sCommonRegs.OENR |= (out << (tu * 2));
+{
+ if(out == OUT1){
+
+ switch(tu){
+
+ case TIMA:
+ LL_HRTIM_EnableOutput(HRTIM1, LL_HRTIM_OUTPUT_TA1);
+ break;
+
+ case TIMB:
+ LL_HRTIM_EnableOutput(HRTIM1, LL_HRTIM_OUTPUT_TB1);
+ break;
+
+ case TIMC:
+ LL_HRTIM_EnableOutput(HRTIM1, LL_HRTIM_OUTPUT_TC1);
+ break;
+
+ case TIMD:
+ LL_HRTIM_EnableOutput(HRTIM1, LL_HRTIM_OUTPUT_TD1);
+ break;
+
+ case TIME:
+ LL_HRTIM_EnableOutput(HRTIM1, LL_HRTIM_OUTPUT_TE1);
+ break;
+
+ case TIMF:
+ LL_HRTIM_EnableOutput(HRTIM1, LL_HRTIM_OUTPUT_TF1);
+ break;
+
+ default:
+ break;
+
+ }
+
+ }else{
+
+ switch(tu){
+
+ case TIMA:
+ LL_HRTIM_EnableOutput(HRTIM1, LL_HRTIM_OUTPUT_TA2);
+ break;
+
+ case TIMB:
+ LL_HRTIM_EnableOutput(HRTIM1, LL_HRTIM_OUTPUT_TB2);
+ break;
+
+ case TIMC:
+ LL_HRTIM_EnableOutput(HRTIM1, LL_HRTIM_OUTPUT_TC2);
+ break;
+
+ case TIMD:
+ LL_HRTIM_EnableOutput(HRTIM1, LL_HRTIM_OUTPUT_TD2);
+ break;
+
+ case TIME:
+ LL_HRTIM_EnableOutput(HRTIM1, LL_HRTIM_OUTPUT_TE2);
+ break;
+
+ case TIMF:
+ LL_HRTIM_EnableOutput(HRTIM1, LL_HRTIM_OUTPUT_TF2);
+ break;
+
+ default:
+ break;
+
+
+ }
+
+ }
+
}
+
void hrtim_out_dis(hrtim_t hrtim, hrtim_tu_t tu, hrtim_out_t out)
{
- dev(hrtim)->sCommonRegs.ODISR |= (out << (tu * 2));
+ if(out == OUT1){
+
+ switch(tu){
+
+ case TIMA:
+ LL_HRTIM_DisableOutput(HRTIM1, LL_HRTIM_OUTPUT_TA1);
+ break;
+
+ case TIMB:
+ LL_HRTIM_DisableOutput(HRTIM1, LL_HRTIM_OUTPUT_TB1);
+ break;
+
+ case TIMC:
+ LL_HRTIM_DisableOutput(HRTIM1, LL_HRTIM_OUTPUT_TC1);
+ break;
+
+ case TIMD:
+ LL_HRTIM_DisableOutput(HRTIM1, LL_HRTIM_OUTPUT_TD1);
+ break;
+
+ case TIME:
+ LL_HRTIM_DisableOutput(HRTIM1, LL_HRTIM_OUTPUT_TE1);
+ break;
+
+ case TIMF:
+ LL_HRTIM_DisableOutput(HRTIM1, LL_HRTIM_OUTPUT_TF1);
+ break;
+
+ default:
+ break;
+
+ }
+
+ }else{
+
+ switch(tu){
+
+ case TIMA:
+ LL_HRTIM_DisableOutput(HRTIM1, LL_HRTIM_OUTPUT_TA2);
+ break;
+
+ case TIMB:
+ LL_HRTIM_DisableOutput(HRTIM1, LL_HRTIM_OUTPUT_TB2);
+ break;
+
+ case TIMC:
+ LL_HRTIM_DisableOutput(HRTIM1, LL_HRTIM_OUTPUT_TC2);
+ break;
+
+ case TIMD:
+ LL_HRTIM_DisableOutput(HRTIM1, LL_HRTIM_OUTPUT_TD2);
+ break;
+
+ case TIME:
+ LL_HRTIM_DisableOutput(HRTIM1, LL_HRTIM_OUTPUT_TE2);
+ break;
+
+ case TIMF:
+ LL_HRTIM_DisableOutput(HRTIM1, LL_HRTIM_OUTPUT_TF2);
+ break;
+
+ default:
+ break;
+
+
+ }
+
+ }
}
@@ -495,13 +787,13 @@ void hrtim_pwm_dt(hrtim_t hrtim, hrtim_tu_t tu, uint16_t ns)
uint32_t ps = ns * 1000;
/* t_dtg = (2^dtpsc) * (t_hrtim / 8)
* = (2^dtpsc) / (f_hrtim * 8) */
-#if defined(CONFIG_SOC_SERIES_STM32F3X)
- uint32_t f_hrtim = hrtim_get_apb2_clock() * 2;
-#elif defined(CONFIG_SOC_SERIES_STM32G4X)
- uint32_t f_hrtim = hrtim_get_apb2_clock();
-#else
-#warning "unsupported stm32XX family"
-#endif
+ #if defined(CONFIG_SOC_SERIES_STM32F3X)
+ uint32_t f_hrtim = hrtim_get_apb2_clock() * 2;
+ #elif defined(CONFIG_SOC_SERIES_STM32G4X)
+ uint32_t f_hrtim = hrtim_get_apb2_clock();
+ #else
+ #warning "unsupported stm32XX family"
+ #endif
uint8_t dtpsc = 0; // Deadtime clock prescaler set at xx
uint32_t t_dtg_ps = (1 << dtpsc) * 1000000 / ((f_hrtim * 8) / 1000000); // intermediate gain for dead time calculation
@@ -514,22 +806,25 @@ void hrtim_pwm_dt(hrtim_t hrtim, hrtim_tu_t tu, uint16_t ns)
if (dt > 511) {
dt = 511;
}
- dev(hrtim)->sTimerxRegs[tu].DTxR &= ~(HRTIM_DTR_DTPRSC_Msk
- | HRTIM_DTR_DTF_Msk
- | HRTIM_DTR_DTR);
- dev(hrtim)->sTimerxRegs[tu].DTxR |= (dtpsc << HRTIM_DTR_DTPRSC_Pos); // Deadtime clock prescaler
- dev(hrtim)->sTimerxRegs[tu].DTxR |= (dt << HRTIM_DTR_DTF_Pos); // Deadtime falling edge value
- dev(hrtim)->sTimerxRegs[tu].DTxR |= (dt << HRTIM_DTR_DTR_Pos); // Deadtime rising edge value
-// dev(hrtim)->sTimerxRegs[tu].DTxR |= HRTIM_DTR_SDTF; //change the behavior of the deadtime insertion by overlapping the signals (negative falling edge)
-// dev(hrtim)->sTimerxRegs[tu].DTxR |= HRTIM_DTR_SDTR; //change the behavior of the deadtime insertion by overlapping the signals (positive falling edge)
- dev(hrtim)->sTimerxRegs[tu].OUTxR |= HRTIM_OUTR_DTEN; /* Note: This
+
+ LL_HRTIM_DT_SetPrescaler(HRTIM1, tu, dtpsc ); // Deadtime clock prescaler
+
+ LL_HRTIM_DT_SetFallingValue(HRTIM1, tu, dt); // Deadtime falling edge value
+
+ LL_HRTIM_DT_SetRisingValue(HRTIM1, tu, dt); // Deadtime rising edge value
+
+ // LL_HRTIM_DT_SetFallingSign(hrtim, tu, LL_HRTIM_DT_FALLING_NEGATIVE); // Change the behavior of the deadtime insertion by overlapping the signals (negative falling edge)
+
+ // LL_HRTIM_DT_SetRisingSign(hrtim, tu, LL_HRTIM_DT_RISING_POSITIVE); // change the behavior of the deadtime insertion by overlapping the signals (positive falling edge)
+
+ LL_HRTIM_TIM_EnableDeadTime(HRTIM1, tu); /* Note: This
* parameter cannot be changed once the timer is operating (TxEN bit
* set) or if its outputs are enabled and set/reset by another timer. */
}
void hrtim_adc_trigger_set_postscaler(hrtim_t hrtim, uint32_t ps_ratio)
{
- dev(hrtim)->sCommonRegs.ADCPS1 |= ps_ratio;
+ LL_HRTIM_SetADCPostScaler(HRTIM1, LL_HRTIM_ADCTRIG_1,ps_ratio);
}
void hrtim_adc_trigger_en(uint32_t event_number, uint32_t source_timer, uint32_t event)
@@ -573,16 +868,18 @@ void hrtim_adc_trigger_en(uint32_t event_number, uint32_t source_timer, uint32_t
LL_HRTIM_SetADCTrigUpdate(HRTIM1, adcTrig, update);
}
-void hrtim_adc_trigger_dis(hrtim_t hrtim, hrtim_adc_t adc, hrtim_adc_trigger_t evt)
+void hrtim_adc_trigger_dis(hrtim_t hrtim, hrtim_adc_t adc, uint32_t evt)
{
switch (adc) {
- case ADC1R: dev(hrtim)->sCommonRegs.ADC1R &= ~evt; break;
- case ADC2R: dev(hrtim)->sCommonRegs.ADC2R &= ~evt; break;
- case ADC3R: dev(hrtim)->sCommonRegs.ADC3R &= ~evt; break;
- case ADC4R: dev(hrtim)->sCommonRegs.ADC4R &= ~evt; break;
+
+ case ADC1R: LL_HRTIM_SetADCTrigSrc(HRTIM1, LL_HRTIM_ADCTRIG_1,LL_HRTIM_GetADCTrigSrc(HRTIM1,LL_HRTIM_ADCTRIG_1)&~ evt);
+ case ADC2R: LL_HRTIM_SetADCTrigSrc(HRTIM1, LL_HRTIM_ADCTRIG_2, LL_HRTIM_GetADCTrigSrc(HRTIM1,LL_HRTIM_ADCTRIG_2)&~ evt);
+ case ADC3R: LL_HRTIM_SetADCTrigSrc(HRTIM1, LL_HRTIM_ADCTRIG_3,LL_HRTIM_GetADCTrigSrc(HRTIM1,LL_HRTIM_ADCTRIG_3)&~ evt);
+ case ADC4R: LL_HRTIM_SetADCTrigSrc(HRTIM1, LL_HRTIM_ADCTRIG_4, LL_HRTIM_GetADCTrigSrc(HRTIM1,LL_HRTIM_ADCTRIG_4)&~ evt);
}
}
+
int hrtim_get_apb2_clock()
{
int prescaler = 1;
@@ -608,3 +905,4 @@ int hrtim_get_apb2_clock()
return CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC / prescaler;
}
+
diff --git a/zephyr/modules/owntech_hrtim_driver/zephyr/src/voltage_mode/hrtim_voltage_mode.h b/zephyr/modules/owntech_hrtim_driver/zephyr/src/voltage_mode/hrtim_voltage_mode.h
index cc3d861..8bb51c3 100644
--- a/zephyr/modules/owntech_hrtim_driver/zephyr/src/voltage_mode/hrtim_voltage_mode.h
+++ b/zephyr/modules/owntech_hrtim_driver/zephyr/src/voltage_mode/hrtim_voltage_mode.h
@@ -31,6 +31,7 @@
* @author Clément Foucher <clement.foucher@laas.fr>
* @author Antoine Boche <antoine.boche@laas.fr>
* @author Luiz Villa <luiz.villa@laas.fr>
+ * @author Ayoub Farah Hassan <ayoub.farah-hassan@laas.fr>
*/
#ifndef HRTIM_VOLTAGE_MODE_H_
@@ -38,6 +39,7 @@
#include <stdint.h>
#include <limits.h>
+#include <stm32_ll_hrtim.h>
#include <pinmux/pinmux_stm32.h>
@@ -65,44 +67,6 @@ extern "C" {
#define HRTIM_UNDEF (UINT_MAX)
#endif
-/**
- * @brief HRTIM Set/Reset trigger definition
- */
-typedef enum {
- SOFT_TRIG = 0x00000001, /*< Software Set/Reset trigger */
- RESYNC = 0x00000002, /*< Timer x resynchronization */
- PER = 0x00000004, /*< Timer x Period */
- CMP1 = 0x00000008, /*< Timer x Compare 1 */
- CMP2 = 0x00000010, /*< Timer x Compare 2 */
- CMP3 = 0x00000020, /*< Timer x Compare 3 */
- CMP4 = 0x00000040, /*< Timer x Compare 4 */
- MSTPER = 0x00000080, /*< Master Period */
- MSTCMP1 = 0x00000100, /*< Master Compare 1 */
- MSTCMP2 = 0x00000200, /*< Master Compare 2 */
- MSTCMP3 = 0x00000400, /*< Master Compare 3 */
- MSTCMP4 = 0x00000800, /*< Master Compare 4 */
- TIMEVNT1 = 0x00001000, /*< Timer Event 1 */
- TIMEVNT2 = 0x00002000, /*< Timer Event 2 */
- TIMEVNT3 = 0x00004000, /*< Timer Event 3 */
- TIMEVNT4 = 0x00008000, /*< Timer Event 4 */
- TIMEVNT5 = 0x00010000, /*< Timer Event 5 */
- TIMEVNT6 = 0x00020000, /*< Timer Event 6 */
- TIMEVNT7 = 0x00040000, /*< Timer Event 7 */
- TIMEVNT8 = 0x00080000, /*< Timer Event 8 */
- TIMEVNT9 = 0x00100000, /*< Timer Event 9 */
- EXTEVNT1 = 0x00200000, /*< External Event 1 */
- EXTEVNT2 = 0x00400000, /*< External Event 2 */
- EXTEVNT3 = 0x00800000, /*< External Event 3 */
- EXTEVNT4 = 0x01000000, /*< External Event 4 */
- EXTEVNT5 = 0x02000000, /*< External Event 5 */
- EXTEVNT6 = 0x04000000, /*< External Event 6 */
- EXTEVNT7 = 0x08000000, /*< External Event 7 */
- EXTEVNT8 = 0x10000000, /*< External Event 8 */
- EXTEVNT9 = 0x20000000, /*< External Event 9 */
- EXTEVNT10 = 0x40000000, /*< External Event 10 */
- UPDATE = 0x80000000 /*< Registers update (transfer preload
- to active) */
-} hrtim_cb_t;
/**
* @brief HRTIM comparators definition
@@ -118,136 +82,14 @@ typedef enum {
MCMP4R = 4
} hrtim_cmp_t;
-/**
- * @brief HRTIM outputs definition
- */
-typedef enum {
- OUT1 = 1,
+
+
+typedef enum{
+
+ OUT1 = 1,
OUT2 = 2
} hrtim_out_t;
-/**
- * @brief HRTIM Timerx reset event definition
- *
- * Note: Bit definitions in stm32xxxx.h are for RSTAR (Timer A)
- * where Bits 19:30 are reset signals come from TIMB, TIMC,
- * TIMD, TIME so they are not usable for another unit.
- */
-typedef enum {
- RST_UPDT = 0x00000002, /*< Timer x Update reset */
- RST_CMP2 = 0x00000004, /*< Timer x compare 2 reset */
- RST_CMP4 = 0x00000008, /*< Timer x compare 4 reset */
- RST_MSTPER = 0x00000010, /*< Master timer Period */
- RST_MSTCMP1 = 0x00000020, /*< Master Compare 1 */
- RST_MSTCMP2 = 0x00000040, /*< Master Compare 2 */
- RST_MSTCMP3 = 0x00000080, /*< Master Compare 3 */
- RST_MSTCMP4 = 0x00000100, /*< Master Compare 4 */
- RST_EXTEVNT1 = 0x00000200, /*< External Event 1 */
- RST_EXTEVNT2 = 0x00000400, /*< External Event 2 */
- RST_EXTEVNT3 = 0x00000800, /*< External Event 3 */
- RST_EXTEVNT4 = 0x00001000, /*< External Event 4 */
- RST_EXTEVNT5 = 0x00002000, /*< External Event 5 */
- RST_EXTEVNT6 = 0x00004000, /*< External Event 6 */
- RST_EXTEVNT7 = 0x00008000, /*< External Event 7 */
- RST_EXTEVNT8 = 0x00010000, /*< External Event 8 */
- RST_EXTEVNT9 = 0x00020000, /*< External Event 9 */
- RST_EXTEVNT10 = 0x00040000, /*< External Event 10 */
- RSTA_TBCMP1 = 0x00080000, /*< Timer B Compare 1 for TIMA */
- RSTA_TBCMP2 = 0x00100000, /*< Timer B Compare 2 for TIMA */
- RSTA_TBCMP4 = 0x00200000, /*< Timer B Compare 4 for TIMA */
- RSTA_TCCMP1 = 0x00400000, /*< Timer C Compare 1 for TIMA */
- RSTA_TCCMP2 = 0x00800000, /*< Timer C Compare 2 for TIMA */
- RSTA_TCCMP4 = 0x01000000, /*< Timer C Compare 4 for TIMA */
- RSTA_TDCMP1 = 0x02000000, /*< Timer D Compare 1 for TIMA */
- RSTA_TDCMP2 = 0x04000000, /*< Timer D Compare 2 for TIMA */
- RSTA_TDCMP4 = 0x08000000, /*< Timer D Compare 4 for TIMA */
- RSTA_TECMP1 = 0x10000000, /*< Timer E Compare 1 for TIMA */
- RSTA_TECMP2 = 0x20000000, /*< Timer E Compare 2 for TIMA */
- RSTA_TECMP4 = 0x40000000, /*< Timer E Compare 4 for TIMA */
- RSTB_TACMP1 = 0x00080000, /*< Timer A Compare 1 for TIMB */
- RSTB_TACMP2 = 0x00100000, /*< Timer A Compare 2 for TIMB */
- RSTB_TACMP4 = 0x00200000, /*< Timer A Compare 4 for TIMB */
- RSTB_TCCMP1 = 0x00400000, /*< Timer C Compare 1 for TIMB */
- RSTB_TCCMP2 = 0x00800000, /*< Timer C Compare 2 for TIMB */
- RSTB_TCCMP4 = 0x01000000, /*< Timer C Compare 4 for TIMB */
- RSTB_TDCMP1 = 0x02000000, /*< Timer D Compare 1 for TIMB */
- RSTB_TDCMP2 = 0x04000000, /*< Timer D Compare 2 for TIMB */
- RSTB_TDCMP4 = 0x08000000, /*< Timer D Compare 4 for TIMB */
- RSTB_TECMP1 = 0x10000000, /*< Timer E Compare 1 for TIMB */
- RSTB_TECMP2 = 0x20000000, /*< Timer E Compare 2 for TIMB */
- RSTB_TECMP4 = 0x40000000, /*< Timer E Compare 4 for TIMB */
- RSTC_TACMP1 = 0x00080000, /*< Timer A Compare 1 for TIMC */
- RSTC_TACMP2 = 0x00100000, /*< Timer A Compare 2 for TIMC */
- RSTC_TACMP4 = 0x00200000, /*< Timer A Compare 4 for TIMC */
- RSTC_TBCMP1 = 0x00400000, /*< Timer B Compare 1 for TIMC */
- RSTC_TBCMP2 = 0x00800000, /*< Timer B Compare 2 for TIMC */
- RSTC_TBCMP4 = 0x01000000, /*< Timer B Compare 4 for TIMC */
- RSTC_TDCMP1 = 0x02000000, /*< Timer D Compare 1 for TIMC */
- RSTC_TDCMP2 = 0x04000000, /*< Timer D Compare 2 for TIMC */
- RSTC_TDCMP4 = 0x08000000, /*< Timer D Compare 4 for TIMC */
- RSTC_TECMP1 = 0x10000000, /*< Timer E Compare 1 for TIMC */
- RSTC_TECMP2 = 0x20000000, /*< Timer E Compare 2 for TIMC */
- RSTC_TECMP4 = 0x40000000, /*< Timer E Compare 4 for TIMC */
- RSTD_TACMP1 = 0x00080000, /*< Timer A Compare 1 for TIMD */
- RSTD_TACMP2 = 0x00100000, /*< Timer A Compare 2 for TIMD */
- RSTD_TACMP4 = 0x00200000, /*< Timer A Compare 4 for TIMD */
- RSTD_TBCMP1 = 0x00400000, /*< Timer B Compare 1 for TIMD */
- RSTD_TBCMP2 = 0x00800000, /*< Timer B Compare 2 for TIMD */
- RSTD_TBCMP4 = 0x01000000, /*< Timer B Compare 4 for TIMD */
- RSTD_TCCMP1 = 0x02000000, /*< Timer C Compare 1 for TIMD */
- RSTD_TCCMP2 = 0x04000000, /*< Timer C Compare 2 for TIMD */
- RSTD_TCCMP4 = 0x08000000, /*< Timer C Compare 4 for TIMD */
- RSTD_TECMP1 = 0x10000000, /*< Timer E Compare 1 for TIMD */
- RSTD_TECMP2 = 0x20000000, /*< Timer E Compare 2 for TIMD */
- RSTD_TECMP4 = 0x40000000, /*< Timer E Compare 4 for TIMD */
- RSTE_TACMP1 = 0x00080000, /*< Timer A Compare 1 for TIME */
- RSTE_TACMP2 = 0x00100000, /*< Timer A Compare 2 for TIME */
- RSTE_TACMP4 = 0x00200000, /*< Timer A Compare 4 for TIME */
- RSTE_TBCMP1 = 0x00400000, /*< Timer B Compare 1 for TIME */
- RSTE_TBCMP2 = 0x00800000, /*< Timer B Compare 2 for TIME */
- RSTE_TBCMP4 = 0x01000000, /*< Timer B Compare 4 for TIME */
- RSTE_TCCMP1 = 0x02000000, /*< Timer C Compare 1 for TIME */
- RSTE_TCCMP2 = 0x04000000, /*< Timer C Compare 2 for TIME */
- RSTE_TCCMP4 = 0x08000000, /*< Timer C Compare 4 for TIME */
- RSTE_TDCMP1 = 0x10000000, /*< Timer D Compare 1 for TIME */
- RSTE_TDCMP2 = 0x20000000, /*< Timer D Compare 2 for TIME */
- RSTE_TDCMP4 = 0x40000000, /*< Timer D Compare 4 for TIME */
-#if (HRTIM_STU_NUMOF == 6)
- RSTA_TFCMP2 = 0x80000000, /*< Timer F Compare 2 for TIMA */
- RSTB_TFCMP2 = 0x80000000, /*< Timer F Compare 2 for TIMB */
- RSTC_TFCMP2 = 0x80000000, /*< Timer F Compare 2 for TIMC */
- RSTD_TFCMP2 = 0x80000000, /*< Timer F Compare 2 for TIMD */
- RSTE_TFCMP2 = 0x80000000, /*< Timer F Compare 2 for TIME */
- RSTF_TACMP1 = 0x00080000, /*< Timer A Compare 1 for TIMF */
- RSTF_TACMP2 = 0x00100000, /*< Timer A Compare 2 for TIMF */
- RSTF_TACMP4 = 0x00200000, /*< Timer A Compare 4 for TIMF */
- RSTF_TBCMP1 = 0x00400000, /*< Timer B Compare 1 for TIMF */
- RSTF_TBCMP2 = 0x00800000, /*< Timer B Compare 2 for TIMF */
- RSTF_TBCMP4 = 0x01000000, /*< Timer B Compare 4 for TIMF */
- RSTF_TCCMP1 = 0x02000000, /*< Timer C Compare 1 for TIMF */
- RSTF_TCCMP2 = 0x04000000, /*< Timer C Compare 2 for TIMF */
- RSTF_TCCMP4 = 0x08000000, /*< Timer C Compare 4 for TIMF */
- RSTF_TDCMP1 = 0x10000000, /*< Timer D Compare 1 for TIMF */
- RSTF_TDCMP2 = 0x20000000, /*< Timer D Compare 2 for TIMF */
- RSTF_TDCMP4 = 0x40000000, /*< Timer D Compare 4 for TIMF */
- RSTF_TECMP2 = 0x80000000, /*< Timer E Compare 2 for TIMF */
-#endif
-} hrtim_rst_evt_t;
-
-/**
- * @brief HRTIM timing units CEN bits
- */
-typedef enum {
- MCEN = HRTIM_MCR_MCEN,
- TACEN = HRTIM_MCR_TACEN,
- TBCEN = HRTIM_MCR_TBCEN,
- TCCEN = HRTIM_MCR_TCCEN,
- TDCEN = HRTIM_MCR_TDCEN,
- TECEN = HRTIM_MCR_TECEN,
-#if (HRTIM_STU_NUMOF == 6)
- TFCEN = HRTIM_MCR_TFCEN
-#endif
-} hrtim_cen_t;
/**
* @brief HRTIM ADC trigger registers definition
@@ -259,204 +101,488 @@ typedef enum {
ADC4R = 4
} hrtim_adc_t;
+
/**
- * @brief HRTIM ADC trigger register bits definitions
+ * @brief HRTIM counting mode setting
+ *
*/
typedef enum {
- AD13_MC1 = 0x00000001, /*< ADC trigger on master compare 1 */
- AD13_MC2 = 0x00000002, /*< ADC trigger on master compare 2 */
- AD13_MC3 = 0x00000004, /*< ADC trigger on master compare 3 */
- AD13_MC4 = 0x00000008, /*< ADC trigger on master compare 4 */
- AD13_MPER = 0x00000010, /*< ADC trigger on master period */
- AD13_EEV1 = 0x00000020, /*< ADC trigger on external event 1 */
- AD13_EEV2 = 0x00000040, /*< ADC trigger on external event 2 */
- AD13_EEV3 = 0x00000080, /*< ADC trigger on external event 3 */
- AD13_EEV4 = 0x00000100, /*< ADC trigger on external event 4 */
- AD13_EEV5 = 0x00000200, /*< ADC trigger on external event 5 */
- AD13_TFC2 = 0x00000400, /*< ADC trigger on timer F compare 2 */
- AD13_TAC3 = 0x00000800, /*< ADC trigger on timer A compare 3 */
- AD13_TAC4 = 0x00001000, /*< ADC trigger on timer A compare 4 */
- AD13_TAPER = 0x00002000, /*< ADC trigger on timer A period */
- AD13_TARST = 0x00004000, /*< ADC trigger on timer A reset */
- AD13_TFC3 = 0x00008000, /*< ADC trigger on timer F compare 3 */
- AD13_TBC3 = 0x00010000, /*< ADC trigger on timer B compare 3 */
- AD13_TBC4 = 0x00020000, /*< ADC trigger on timer B compare 4 */
- AD13_TBPER = 0x00040000, /*< ADC trigger on timer B period */
- AD13_TBRST = 0x00080000, /*< ADC trigger on timer B reset */
- AD13_TFC4 = 0x00100000, /*< ADC trigger on timer F compare 4 */
- AD13_TCC3 = 0x00200000, /*< ADC trigger on timer C compare 3 */
- AD13_TCC4 = 0x00400000, /*< ADC trigger on timer C compare 4 */
- AD13_TCPER = 0x00800000, /*< ADC trigger on timer C period */
- AD13_TFPER = 0x01000000, /*< ADC trigger on timer F period */
- AD13_TDC3 = 0x02000000, /*< ADC trigger on timer D compare 3 */
- AD13_TDC4 = 0x04000000, /*< ADC trigger on timer D compare 4 */
- AD13_TDPER = 0x08000000, /*< ADC trigger on timer D period */
- AD13_TFRST = 0x10000000, /*< ADC trigger on timer F reset */
- AD13_TEC3 = 0x20000000, /*< ADC trigger on timer E compare 3 */
- AD13_TEC4 = 0x40000000, /*< ADC trigger on timer E compare 4 */
- AD13_TEPER = 0x80000000, /*< ADC trigger on timer E period */
-
- AD24_MC1 = 0x00000001, /*< ADC trigger on master compare 1 */
- AD24_MC2 = 0x00000002, /*< ADC trigger on master compare 2 */
- AD24_MC3 = 0x00000004, /*< ADC trigger on master compare 3 */
- AD24_MC4 = 0x00000008, /*< ADC trigger on master compare 4 */
- AD24_MPER = 0x00000010, /*< ADC trigger on master period */
- AD24_EEV6 = 0x00000020, /*< ADC trigger on external event 6 */
- AD24_EEV7 = 0x00000040, /*< ADC trigger on external event 7 */
- AD24_EEV8 = 0x00000080, /*< ADC trigger on external event 8 */
- AD24_EEV9 = 0x00000100, /*< ADC trigger on external event 9 */
- AD24_EEV10 = 0x00000200, /*< ADC trigger on external event 10 */
- AD24_TAC2 = 0x00000400, /*< ADC trigger on timer A compare 2 */
- AD24_TFC2 = 0x00000800, /*< ADC trigger on timer F compare 2 */
- AD24_TAC4 = 0x00001000, /*< ADC trigger on timer A compare 4 */
- AD24_TAPER = 0x00002000, /*< ADC trigger on timer A period */
- AD24_TBC2 = 0x00004000, /*< ADC trigger on timer B compare 2 */
- AD24_TFC3 = 0x00008000, /*< ADC trigger on timer F compare 3 */
- AD24_TBC4 = 0x00010000, /*< ADC trigger on timer B compare 4 */
- AD24_TBPER = 0x00020000, /*< ADC trigger on timer B period */
- AD24_TCC2 = 0x00040000, /*< ADC trigger on timer C compare 2 */
- AD24_TFC4 = 0x00080000, /*< ADC trigger on timer F compare 4 */
- AD24_TCC4 = 0x00100000, /*< ADC trigger on timer C compare 4 */
- AD24_TCPER = 0x00200000, /*< ADC trigger on timer C period */
- AD24_TCRST = 0x00400000, /*< ADC trigger on timer C reset */
- AD24_TDC2 = 0x00800000, /*< ADC trigger on timer D compare 2 */
- AD24_TFPER = 0x01000000, /*< ADC trigger on timer F period */
- AD24_TDC4 = 0x02000000, /*< ADC trigger on timer D compare 4 */
- AD24_TDPER = 0x04000000, /*< ADC trigger on timer D period */
- AD24_TDRST = 0x08000000, /*< ADC trigger on timer D reset */
- AD24_TEC2 = 0x10000000, /*< ADC trigger on timer E compare 2 */
- AD24_TEC3 = 0x20000000, /*< ADC trigger on timer E compare 3 */
- AD24_TEC4 = 0x40000000, /*< ADC trigger on timer E compare 4 */
- AD24_TERST = 0x80000000, /*< ADC trigger on timer E reset */
-} hrtim_adc_trigger_t;
+
+ Lft_aligned =1,
+ UpDwn = 2
+
+}hrtim_cnt_t;
+
+
/**
* @brief Initialize an HRTIM device and all these timing units for
* complementary pwm outputs with a dead time.
*
- * @param[in] dev HRTIM device to initialize
- * @param[inout] freq HRTIM frequency in Hz
- * @param[in] dt Desired dead time in ns
- * @param[in] leg1_upper_switch_convention Choice of the switch convention for leg 1
- * @param[in] leg2_upper_switch_convention Choice of the switch convention for leg 2
- *
- * @return actual HRTIM resolution on success
- * @return 0 on error
+ * @param[in] dev HRTIM device to initialize
+ * @param[inout] freq HRTIM frequency in Hz
+ * @param[in] dt Desired dead time in ns
+ * @param[in] leg1_upper_switch_convention Choice of the switch convention for leg 1, can be one of the following values:
+ * @arg @ref True (Buck mode)
+ * @arg @ref False (Boost mode)
+ * @param[in] leg2_upper_switch_convention Choice of the switch convention for leg 2, can be one of the following values:
+ * @arg @ref True (Buck mode)
+ * @arg @ref False (Boost mode)
+ * @return actual HRTIM resolution on success
+ * @return 0 on error
*/
uint16_t hrtim_init(hrtim_t dev, uint32_t *freq, uint16_t dt, uint8_t leg1_upper_switch_convention, uint8_t leg2_upper_switch_convention);
+
+/**
+ * @brief Initialize an HRTIM device and all these timing units for
+ * complementary pwm outputs with a dead time with Up-Down mode (center alligned).
+ *
+ * @param[in] dev HRTIM device to initialize
+ * @param[inout] freq HRTIM frequency in Hz
+ * @param[in] dt Desired dead time in ns
+ * @param[in] leg1_upper_switch_convention Choice of the switch convention for leg 1, can be one of the following values:
+ * @arg @ref True (Buck mode)
+ * @arg @ref False (Boost mode)
+ * @param[in] leg2_upper_switch_convention Choice of the switch convention for leg 2, can be one of the following values:
+ * @arg @ref True (Buck mode)
+ * @arg @ref False (Boost mode)
+ * @return actual HRTIM resolution on success
+ * @return 0 on error
+ */
+uint16_t hrtim_init_updwn(hrtim_t dev, uint32_t *freq, uint16_t dt, uint8_t leg1_upper_switch_convention, uint8_t leg2_upper_switch_convention);
+
+
/**
* @brief Initialize an HRTIM device master timer
*
- * @param[in] dev HRTIM device to initialize
- * @param[inout] freq HRTIM frequency in Hz
+ * @param[in] dev HRTIM device to initialize
+ * @param[inout] freq HRTIM frequency in Hz
*
- * @return actual HRTIM resolution on success
- * @return 0 on error
+ * @return actual HRTIM resolution on success
+ * @return 0 on error
*/
uint16_t hrtim_init_master(hrtim_t dev, uint32_t *freq);
/**
* @brief Initialize a timing unit
*
- * @param[in] dev HRTIM device
- * @param[in] tu Timing unit to initialize
- * @param[inout] freq HRTIM frequency in Hz
+ * @param[in] dev HRTIM device
+ * @param[in] tu Timing unit to initialize, can be one of the following values:
+ * @arg @ref TIMA
+ * @arg @ref TIMB
+ * @arg @ref TIMC
+ * @arg @ref TIMD
+ * @arg @ref TIME
+ * @arg @ref TIMF
+ * @param[in] cnt_mode Counting mode
+ * @arg @ref Lft_aligned
+ * @arg @ref UpDwn
+ * @param[inout] freq HRTIM frequency in Hz
*
- * @return actual timing unit resolution on success
- * @return 0 on error
+ * @return actual timing unit resolution on success
+ * @return 0 on error
*/
-uint16_t hrtim_init_tu(hrtim_t dev, hrtim_tu_t tu, uint32_t *freq);
+uint16_t hrtim_init_tu(hrtim_t dev, hrtim_tu_t tu, uint32_t *freq, hrtim_cnt_t cnt_mode);
/**
* @brief Set crossbar(s) setting
*
- * @param[in] dev HRTIM device
- * @param[in] tu Timing unit
- * @param[in] out Output 1 or 2
- * @param[in] cb Set crossbar(s)
- */
-void hrtim_set_cb_set(hrtim_t dev, hrtim_tu_t tu, hrtim_out_t out,
- hrtim_cb_t cb);
+ * @param[in] dev HRTIM device
+ * @param[in] out Output, can be one of the following values:
+ * @arg @ref LL_HRTIM_OUTPUT_TA1
+ * @arg @ref LL_HRTIM_OUTPUT_TA2
+ * @arg @ref LL_HRTIM_OUTPUT_TB1
+ * @arg @ref LL_HRTIM_OUTPUT_TB2
+ * @arg @ref LL_HRTIM_OUTPUT_TC1
+ * @arg @ref LL_HRTIM_OUTPUT_TC2
+ * @arg @ref LL_HRTIM_OUTPUT_TD1
+ * @arg @ref LL_HRTIM_OUTPUT_TD2
+ * @arg @ref LL_HRTIM_OUTPUT_TE1
+ * @arg @ref LL_HRTIM_OUTPUT_TE2
+ * @arg @ref LL_HRTIM_OUTPUT_TF1
+ * @arg @ref LL_HRTIM_OUTPUT_TF2
+ * @param[in] cb Set crossbar(s)
+ */
+void hrtim_set_cb_set(hrtim_t dev, uint32_t out,
+ uint32_t cb);
/**
* @brief Unset set crossbar(s)
*
- * @param[in] dev HRTIM device
- * @param[in] tu Timing unit
- * @param[in] out Output 1 or 2
- * @param[in] cb Set crossbar(s)
- */
-void hrtim_set_cb_unset(hrtim_t dev, hrtim_tu_t tu, hrtim_out_t out,
- hrtim_cb_t cb);
+ * @param[in] dev HRTIM device
+ * @param[in] out Output, can be one of the following values:
+ * @arg @ref LL_HRTIM_OUTPUT_TA1
+ * @arg @ref LL_HRTIM_OUTPUT_TA2
+ * @arg @ref LL_HRTIM_OUTPUT_TB1
+ * @arg @ref LL_HRTIM_OUTPUT_TB2
+ * @arg @ref LL_HRTIM_OUTPUT_TC1
+ * @arg @ref LL_HRTIM_OUTPUT_TC2
+ * @arg @ref LL_HRTIM_OUTPUT_TD1
+ * @arg @ref LL_HRTIM_OUTPUT_TD2
+ * @arg @ref LL_HRTIM_OUTPUT_TE1
+ * @arg @ref LL_HRTIM_OUTPUT_TE2
+ * @arg @ref LL_HRTIM_OUTPUT_TF1
+ * @arg @ref LL_HRTIM_OUTPUT_TF2
+ * @param[in] cb Set crossbar(s)
+ * @arg @ref LL_HRTIM_OUTPUTSET_NONE
+ * @arg @ref LL_HRTIM_OUTPUTSET_RESYNC
+ * @arg @ref LL_HRTIM_OUTPUTSET_TIMPER
+ * @arg @ref LL_HRTIM_OUTPUTSET_TIMCMP1
+ * @arg @ref LL_HRTIM_OUTPUTSET_TIMCMP2
+ * @arg @ref LL_HRTIM_OUTPUTSET_TIMCMP3
+ * @arg @ref LL_HRTIM_OUTPUTSET_TIMCMP4
+ * @arg @ref LL_HRTIM_OUTPUTSET_MASTERPER
+ * @arg @ref LL_HRTIM_OUTPUTSET_MASTERCMP1
+ * @arg @ref LL_HRTIM_OUTPUTSET_MASTERCMP2
+ * @arg @ref LL_HRTIM_OUTPUTSET_MASTERCMP3
+ * @arg @ref LL_HRTIM_OUTPUTSET_MASTERCMP4
+ * @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV1_TIMBCMP1
+ * @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV2_TIMBCMP2
+ * @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV3_TIMCCMP2
+ * @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV4_TIMCCMP3
+ * @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV5_TIMDCMP1
+ * @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV6_TIMDCMP2
+ * @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV7_TIMECMP3
+ * @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV8_TIMECMP4
+ * @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV9_TIMFCMP4
+ * @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV1_TIMACMP1
+ * @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV2_TIMACMP2
+ * @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV3_TIMCCMP3
+ * @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV4_TIMCCMP4
+ * @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV5_TIMDCMP3
+ * @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV6_TIMDCMP4
+ * @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV7_TIMECMP1
+ * @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV8_TIMECMP2
+ * @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV9_TIMFCMP3
+ * @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV1_TIMACMP2
+ * @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV2_TIMACMP3
+ * @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV3_TIMBCMP2
+ * @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV4_TIMBCMP3
+ * @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV5_TIMDCMP2
+ * @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV6_TIMDCMP4
+ * @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV7_TIMECMP3
+ * @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV8_TIMECMP4
+ * @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV9_TIMFCMP2
+ * @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV1_TIMACMP1
+ * @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV2_TIMACMP4
+ * @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV3_TIMBCMP2
+ * @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV4_TIMBCMP4
+ * @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV5_TIMCCMP4
+ * @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV6_TIMECMP1
+ * @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV7_TIMECMP4
+ * @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV8_TIMFCMP1
+ * @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV9_TIMFCMP3
+ * @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV1_TIMACMP4
+ * @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV2_TIMBCMP3
+ * @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV3_TIMBCMP4
+ * @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV4_TIMCCMP1
+ * @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV5_TIMCCMP2
+ * @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV6_TIMDCMP1
+ * @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV7_TIMDCMP2
+ * @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV8_TIMFCMP3
+ * @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV9_TIMFCMP4
+ * @arg @ref LL_HRTIM_OUTPUTSET_TIMFEV1_TIMACMP3
+ * @arg @ref LL_HRTIM_OUTPUTSET_TIMFEV2_TIMBCMP1
+ * @arg @ref LL_HRTIM_OUTPUTSET_TIMFEV3_TIMBCMP4
+ * @arg @ref LL_HRTIM_OUTPUTSET_TIMFEV4_TIMCCMP1
+ * @arg @ref LL_HRTIM_OUTPUTSET_TIMFEV5_TIMCCMP4
+ * @arg @ref LL_HRTIM_OUTPUTSET_TIMFEV6_TIMDCMP3
+ * @arg @ref LL_HRTIM_OUTPUTSET_TIMFEV7_TIMDCMP4
+ * @arg @ref LL_HRTIM_OUTPUTSET_TIMFEV8_TIMECMP2
+ * @arg @ref LL_HRTIM_OUTPUTSET_TIMFEV9_TIMECMP3
+ * @arg @ref LL_HRTIM_OUTPUTSET_EEV_1
+ * @arg @ref LL_HRTIM_OUTPUTSET_EEV_2
+ * @arg @ref LL_HRTIM_OUTPUTSET_EEV_3
+ * @arg @ref LL_HRTIM_OUTPUTSET_EEV_4
+ * @arg @ref LL_HRTIM_OUTPUTSET_EEV_5
+ * @arg @ref LL_HRTIM_OUTPUTSET_EEV_6
+ * @arg @ref LL_HRTIM_OUTPUTSET_EEV_7
+ * @arg @ref LL_HRTIM_OUTPUTSET_EEV_8
+ * @arg @ref LL_HRTIM_OUTPUTSET_EEV_9
+ * @arg @ref LL_HRTIM_OUTPUTSET_EEV_10
+ * @arg @ref LL_HRTIM_OUTPUTSET_UPDATE
+ * (source = TIMy and destination = TIMx, Compare Unit = CMPz).
+ */
+void hrtim_set_cb_unset(hrtim_t dev, uint32_t out,
+ uint32_t cb);
/**
* @brief Reset crossbar(s) setting
*
- * @param[in] dev HRTIM device
- * @param[in] tu Timing unit
- * @param[in] out Output 1 or 2
- * @param[in] cb Reset crossbar(s)
- */
-void hrtim_rst_cb_set(hrtim_t dev, hrtim_tu_t tu, hrtim_out_t out,
- hrtim_cb_t cb);
+ * @param[in] dev HRTIM device
+ * @param[in] out Output, can be one of the following values:
+ * @arg @ref LL_HRTIM_OUTPUT_TA1
+ * @arg @ref LL_HRTIM_OUTPUT_TA2
+ * @arg @ref LL_HRTIM_OUTPUT_TB1
+ * @arg @ref LL_HRTIM_OUTPUT_TB2
+ * @arg @ref LL_HRTIM_OUTPUT_TC1
+ * @arg @ref LL_HRTIM_OUTPUT_TC2
+ * @arg @ref LL_HRTIM_OUTPUT_TD1
+ * @arg @ref LL_HRTIM_OUTPUT_TD2
+ * @arg @ref LL_HRTIM_OUTPUT_TE1
+ * @arg @ref LL_HRTIM_OUTPUT_TE2
+ * @arg @ref LL_HRTIM_OUTPUT_TF1
+ * @arg @ref LL_HRTIM_OUTPUT_TF2
+ * @param[in] cb Reset crossbar(s), can be one of those following values:
+ * @arg @ref LL_HRTIM_OUTPUTRESET_NONE
+ * @arg @ref LL_HRTIM_OUTPUTRESET_RESYNC
+ * @arg @ref LL_HRTIM_OUTPUTRESET_TIMPER
+ * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCMP1
+ * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCMP2
+ * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCMP3
+ * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCMP4
+ * @arg @ref LL_HRTIM_OUTPUTRESET_MASTERPER
+ * @arg @ref LL_HRTIM_OUTPUTRESET_MASTERCMP1
+ * @arg @ref LL_HRTIM_OUTPUTRESET_MASTERCMP2
+ * @arg @ref LL_HRTIM_OUTPUTRESET_MASTERCMP3
+ * @arg @ref LL_HRTIM_OUTPUTRESET_MASTERCMP4
+ * @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV1_TIMBCMP1
+ * @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV2_TIMBCMP2
+ * @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV3_TIMCCMP2
+ * @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV4_TIMCCMP3
+ * @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV5_TIMDCMP1
+ * @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV6_TIMDCMP2
+ * @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV7_TIMECMP3
+ * @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV8_TIMECMP4
+ * @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV9_TIMFCMP4
+ * @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV1_TIMACMP1
+ * @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV2_TIMACMP2
+ * @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV3_TIMCCMP3
+ * @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV4_TIMCCMP4
+ * @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV5_TIMDCMP3
+ * @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV6_TIMDCMP4
+ * @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV7_TIMECMP1
+ * @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV8_TIMECMP2
+ * @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV9_TIMFCMP3
+ * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV1_TIMACMP2
+ * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV2_TIMACMP3
+ * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV3_TIMBCMP2
+ * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV4_TIMBCMP3
+ * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV5_TIMDCMP2
+ * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV6_TIMDCMP4
+ * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV7_TIMECMP3
+ * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV8_TIMECMP4
+ * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV9_TIMFCMP2
+ * @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV1_TIMACMP1
+ * @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV2_TIMACMP4
+ * @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV3_TIMBCMP2
+ * @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV4_TIMBCMP4
+ * @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV5_TIMCCMP4
+ * @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV6_TIMECMP1
+ * @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV7_TIMECMP4
+ * @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV8_TIMFCMP1
+ * @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV9_TIMFCMP3
+ * @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV1_TIMACMP4
+ * @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV2_TIMBCMP3
+ * @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV3_TIMBCMP4
+ * @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV4_TIMCCMP1
+ * @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV5_TIMCCMP2
+ * @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV6_TIMDCMP1
+ * @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV7_TIMDCMP2
+ * @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV8_TIMFCMP3
+ * @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV9_TIMFCMP4
+ * @arg @ref LL_HRTIM_OUTPUTRESET_TIMFEV1_TIMACMP3
+ * @arg @ref LL_HRTIM_OUTPUTRESET_TIMFEV2_TIMBCMP1
+ * @arg @ref LL_HRTIM_OUTPUTRESET_TIMFEV3_TIMBCMP4
+ * @arg @ref LL_HRTIM_OUTPUTRESET_TIMFEV4_TIMCCMP1
+ * @arg @ref LL_HRTIM_OUTPUTRESET_TIMFEV5_TIMCCMP4
+ * @arg @ref LL_HRTIM_OUTPUTRESET_TIMFEV6_TIMDCMP3
+ * @arg @ref LL_HRTIM_OUTPUTRESET_TIMFEV7_TIMDCMP4
+ * @arg @ref LL_HRTIM_OUTPUTRESET_TIMFEV8_TIMECMP2
+ * @arg @ref LL_HRTIM_OUTPUTRESET_TIMFEV9_TIMECMP3
+ * @arg @ref LL_HRTIM_OUTPUTRESET_EEV_1
+ * @arg @ref LL_HRTIM_OUTPUTRESET_EEV_2
+ * @arg @ref LL_HRTIM_OUTPUTRESET_EEV_3
+ * @arg @ref LL_HRTIM_OUTPUTRESET_EEV_4
+ * @arg @ref LL_HRTIM_OUTPUTRESET_EEV_5
+ * @arg @ref LL_HRTIM_OUTPUTRESET_EEV_6
+ * @arg @ref LL_HRTIM_OUTPUTRESET_EEV_7
+ * @arg @ref LL_HRTIM_OUTPUTRESET_EEV_8
+ * @arg @ref LL_HRTIM_OUTPUTRESET_EEV_9
+ * @arg @ref LL_HRTIM_OUTPUTRESET_EEV_10
+ * @arg @ref LL_HRTIM_OUTPUTRESET_UPDATE
+ * (source = TIMy and destination = TIMx, Compare Unit = CMPz).
+ */
+void hrtim_rst_cb_set(hrtim_t dev, uint32_t out,
+ uint32_t cb);
/**
* @brief Unset reset crossbar(s)
*
- * @param[in] dev HRTIM device
- * @param[in] tu Timing unit
- * @param[in] out Output 1 or 2
- * @param[in] cb Reset crossbar(s)
- */
-void hrtim_rst_cb_unset(hrtim_t dev, hrtim_tu_t tu, hrtim_out_t out,
- hrtim_cb_t cb);
-
-/**
- * @brief Full timing unit outputs set/reset crossbars setting for
- * complementary pwm.
- *
- * @param[in] dev HRTIM device
- * @param[in] tu Timing unit
- * @param[in] switch_convention Choice of the switch convention
+ * @param[in] dev HRTIM device
+ * @param[in] out Output, can be one of the following values:
+ * @arg @ref LL_HRTIM_OUTPUT_TA1
+ * @arg @ref LL_HRTIM_OUTPUT_TA2
+ * @arg @ref LL_HRTIM_OUTPUT_TB1
+ * @arg @ref LL_HRTIM_OUTPUT_TB2
+ * @arg @ref LL_HRTIM_OUTPUT_TC1
+ * @arg @ref LL_HRTIM_OUTPUT_TC2
+ * @arg @ref LL_HRTIM_OUTPUT_TD1
+ * @arg @ref LL_HRTIM_OUTPUT_TD2
+ * @arg @ref LL_HRTIM_OUTPUT_TE1
+ * @arg @ref LL_HRTIM_OUTPUT_TE2
+ * @arg @ref LL_HRTIM_OUTPUT_TF1
+ * @arg @ref LL_HRTIM_OUTPUT_TF2
+ * @param[in] cb Reset crossbar(s), can be one of those following values:
+ * @arg @ref LL_HRTIM_OUTPUTRESET_NONE
+ * @arg @ref LL_HRTIM_OUTPUTRESET_RESYNC
+ * @arg @ref LL_HRTIM_OUTPUTRESET_TIMPER
+ * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCMP1
+ * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCMP2
+ * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCMP3
+ * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCMP4
+ * @arg @ref LL_HRTIM_OUTPUTRESET_MASTERPER
+ * @arg @ref LL_HRTIM_OUTPUTRESET_MASTERCMP1
+ * @arg @ref LL_HRTIM_OUTPUTRESET_MASTERCMP2
+ * @arg @ref LL_HRTIM_OUTPUTRESET_MASTERCMP3
+ * @arg @ref LL_HRTIM_OUTPUTRESET_MASTERCMP4
+ * @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV1_TIMBCMP1
+ * @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV2_TIMBCMP2
+ * @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV3_TIMCCMP2
+ * @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV4_TIMCCMP3
+ * @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV5_TIMDCMP1
+ * @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV6_TIMDCMP2
+ * @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV7_TIMECMP3
+ * @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV8_TIMECMP4
+ * @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV9_TIMFCMP4
+ * @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV1_TIMACMP1
+ * @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV2_TIMACMP2
+ * @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV3_TIMCCMP3
+ * @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV4_TIMCCMP4
+ * @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV5_TIMDCMP3
+ * @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV6_TIMDCMP4
+ * @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV7_TIMECMP1
+ * @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV8_TIMECMP2
+ * @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV9_TIMFCMP3
+ * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV1_TIMACMP2
+ * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV2_TIMACMP3
+ * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV3_TIMBCMP2
+ * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV4_TIMBCMP3
+ * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV5_TIMDCMP2
+ * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV6_TIMDCMP4
+ * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV7_TIMECMP3
+ * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV8_TIMECMP4
+ * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV9_TIMFCMP2
+ * @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV1_TIMACMP1
+ * @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV2_TIMACMP4
+ * @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV3_TIMBCMP2
+ * @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV4_TIMBCMP4
+ * @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV5_TIMCCMP4
+ * @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV6_TIMECMP1
+ * @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV7_TIMECMP4
+ * @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV8_TIMFCMP1
+ * @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV9_TIMFCMP3
+ * @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV1_TIMACMP4
+ * @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV2_TIMBCMP3
+ * @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV3_TIMBCMP4
+ * @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV4_TIMCCMP1
+ * @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV5_TIMCCMP2
+ * @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV6_TIMDCMP1
+ * @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV7_TIMDCMP2
+ * @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV8_TIMFCMP3
+ * @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV9_TIMFCMP4
+ * @arg @ref LL_HRTIM_OUTPUTRESET_TIMFEV1_TIMACMP3
+ * @arg @ref LL_HRTIM_OUTPUTRESET_TIMFEV2_TIMBCMP1
+ * @arg @ref LL_HRTIM_OUTPUTRESET_TIMFEV3_TIMBCMP4
+ * @arg @ref LL_HRTIM_OUTPUTRESET_TIMFEV4_TIMCCMP1
+ * @arg @ref LL_HRTIM_OUTPUTRESET_TIMFEV5_TIMCCMP4
+ * @arg @ref LL_HRTIM_OUTPUTRESET_TIMFEV6_TIMDCMP3
+ * @arg @ref LL_HRTIM_OUTPUTRESET_TIMFEV7_TIMDCMP4
+ * @arg @ref LL_HRTIM_OUTPUTRESET_TIMFEV8_TIMECMP2
+ * @arg @ref LL_HRTIM_OUTPUTRESET_TIMFEV9_TIMECMP3
+ * @arg @ref LL_HRTIM_OUTPUTRESET_EEV_1
+ * @arg @ref LL_HRTIM_OUTPUTRESET_EEV_2
+ * @arg @ref LL_HRTIM_OUTPUTRESET_EEV_3
+ * @arg @ref LL_HRTIM_OUTPUTRESET_EEV_4
+ * @arg @ref LL_HRTIM_OUTPUTRESET_EEV_5
+ * @arg @ref LL_HRTIM_OUTPUTRESET_EEV_6
+ * @arg @ref LL_HRTIM_OUTPUTRESET_EEV_7
+ * @arg @ref LL_HRTIM_OUTPUTRESET_EEV_8
+ * @arg @ref LL_HRTIM_OUTPUTRESET_EEV_9
+ * @arg @ref LL_HRTIM_OUTPUTRESET_EEV_10
+ * @arg @ref LL_HRTIM_OUTPUTRESET_UPDATE
+ * (source = TIMy and destination = TIMx, Compare Unit = CMPz).
+ */
+void hrtim_rst_cb_unset(hrtim_t dev, uint32_t out,
+ uint32_t cb);
+
+/**
+ * @brief Sets up the switching convention of the leg upper switch
+ *
+ * @param[in] hrtim HRTIM device
+ * @param[in] tu Timing unit, can be one of the following values:
+ * @arg @ref TIMA
+ * @arg @ref TIMB
+ * @arg @ref TIMC
+ * @arg @ref TIMD
+ * @arg @ref TIME
+ * @arg @ref TIMF
+ * @param[in] cnt_mode Counting mode
+ * @arg @ref Lft_aligned
+ * @arg @ref UpDwn
+ * @param[in] leg1_upper_switch_convention Choice of the switch convention - 1 for buck mode and 0 for boost mode
*/
-void hrtim_cmpl_pwm_out(hrtim_t dev, hrtim_tu_t tu, bool switch_convention);
+void hrtim_cmpl_pwm_out1(hrtim_t hrtim, hrtim_tu_t tu, bool leg_upper_switch_convention, hrtim_cnt_t cnt_mode);
/**
- * @brief Sets up the switching convention of leg 1
+ * @brief Sets up the switching convention of the leg lower switch
*
- * @param[in] hrtim HRTIM device
- * @param[in] tu Timing unit
+ * @param[in] hrtim HRTIM device
+ * @param[in] tu Timing unit, can be one of the following values:
+ * @arg @ref TIMA
+ * @arg @ref TIMB
+ * @arg @ref TIMC
+ * @arg @ref TIMD
+ * @arg @ref TIME
+ * @arg @ref TIMF
+ * @param[in] cnt_mode Counting mode
+ * @arg @ref Lft_aligned
+ * @arg @ref UpDwn
* @param[in] leg1_upper_switch_convention Choice of the switch convention - 1 for buck mode and 0 for boost mode
- */
-void hrtim_cmpl_pwm_out1(hrtim_t hrtim, hrtim_tu_t tu, bool leg1_upper_switch_convention);
+*/
-/**
- * @brief Sets up the switching convention of leg 2
- *
- * @param[in] hrtim HRTIM device
- * @param[in] tu Timing unit
- * @param[in] leg1_upper_switch_convention Choice of the switch convention - 1 for buck mode and 0 for boost mode
- */
-void hrtim_cmpl_pwm_out2(hrtim_t hrtim, hrtim_tu_t tu, bool leg2_upper_switch_convention);
+void hrtim_cmpl_pwm_out2(hrtim_t hrtim, hrtim_tu_t tu, bool leg_upper_switch_convention, hrtim_cnt_t cnt);
/**
* @brief Set a period value
*
- * @param[in] dev HRTIM device
- * @param[in] tu Timing unit (TIM{A..F} or MSTR for master)
- * @param[in] value Raw value to set
+ * @param[in] dev HRTIM device
+ * @param[in] tu Timing unit, can be one of the following values:
+ * @arg @ref TIMA
+ * @arg @ref TIMB
+ * @arg @ref TIMC
+ * @arg @ref TIMD
+ * @arg @ref TIME
+ * @arg @ref TIMF
+ * @arg @ref MSTR
+ * @param[in] value Raw value to set
*/
void hrtim_period_set(hrtim_t dev, hrtim_tu_t tu, uint16_t value);
/**
* @brief Set a comparator value
*
- * @param[in] dev HRTIM device
- * @param[in] tu Timing unit (TIM{A..F} or MSTR for master)
- * @param[in] cmp Comparator from 1 to 4
- * @param[in] value Raw value to set
+ * @param[in] dev HRTIM device
+ * @param[in] tu Timing unit, can be one of the following values:
+ * @arg @ref TIMA
+ * @arg @ref TIMB
+ * @arg @ref TIMC
+ * @arg @ref TIMD
+ * @arg @ref TIME
+ * @arg @ref TIMF
+ * @arg @ref MSTR
+ * @param[in] cmp Comparator from 1 to 4, can be one of the following values:
+ * @arg @ref CMP1xR
+ * @arg @ref CMP2xR
+ * @arg @ref CMP3xR
+ * @arg @ref CMP4xR
+ * @arg @ref MCMP1R
+ * @arg @ref MCMP2R
+ * @arg @ref MCMP3R
+ * @arg @ref MCMP4R
+ * @param[in] value Raw value to set
*/
void hrtim_cmp_set(hrtim_t dev, hrtim_tu_t tu, hrtim_cmp_t cmp,
uint16_t value);
@@ -464,52 +590,160 @@ void hrtim_cmp_set(hrtim_t dev, hrtim_tu_t tu, hrtim_cmp_t cmp,
/**
* @brief Enable a timing unit counter.
*
- * @param[in] dev HRTIM device
- * @param[in] cen CEN mask
+ * @param[in] dev HRTIM device
+ * @param[in] tu Timing unit, can be one of the following values:
+ * @arg @ref TIMA
+ * @arg @ref TIMB
+ * @arg @ref TIMC
+ * @arg @ref TIMD
+ * @arg @ref TIME
+ * @arg @ref TIMF
+ * @arg @ref MSTR
*/
-void hrtim_cnt_en(hrtim_t dev, hrtim_cen_t cen);
+void hrtim_cnt_en(hrtim_t dev, hrtim_tu_t tu);
/**
* @brief Disable a timing unit counter.
*
- * @param[in] dev HRTIM device
- * @param[in] cen CEN mask
+ * @param[in] dev HRTIM device
+ * @param[in] tu Timing unit, Timing unit, can be one of the following values:
+ * @arg @ref TIMA
+ * @arg @ref TIMB
+ * @arg @ref TIMC
+ * @arg @ref TIMD
+ * @arg @ref TIME
+ * @arg @ref TIMF
+ * @arg @ref MSTR
*/
-void hrtim_cnt_dis(hrtim_t dev, hrtim_cen_t cen);
+void hrtim_cnt_dis(hrtim_t dev, hrtim_tu_t tu);
/**
* @brief Enable a Timerx reset event
*
- * @param[in] dev HRTIM device
- * @param[in] tu Timing unit
- * @param[in] evt Reset event
- */
-void hrtim_rst_evt_en(hrtim_t dev, hrtim_tu_t tu, hrtim_rst_evt_t evt);
-
-/**
- * @brief Disbable a Timerx reset event
- *
- * @param[in] dev HRTIM device
- * @param[in] tu Timing unit
- * @param[in] evt Reset event
- */
-void hrtim_rst_evt_dis(hrtim_t dev, hrtim_tu_t tu, hrtim_rst_evt_t evt);
+ * @param[in] dev HRTIM device
+ * @param[in] tu Timing unit, can be one of the following values:
+ * @arg @ref TIMA
+ * @arg @ref TIMB
+ * @arg @ref TIMC
+ * @arg @ref TIMD
+ * @arg @ref TIME
+ * @arg @ref TIMF
+ * @param[in] evt Reset event, can be one of the following values:
+ * @arg @ref LL_HRTIM_RESETTRIG_NONE
+ * @arg @ref LL_HRTIM_RESETTRIG_UPDATE
+ * @arg @ref LL_HRTIM_RESETTRIG_CMP2
+ * @arg @ref LL_HRTIM_RESETTRIG_CMP4
+ * @arg @ref LL_HRTIM_RESETTRIG_MASTER_PER
+ * @arg @ref LL_HRTIM_RESETTRIG_MASTER_CMP1
+ * @arg @ref LL_HRTIM_RESETTRIG_MASTER_CMP2
+ * @arg @ref LL_HRTIM_RESETTRIG_MASTER_CMP3
+ * @arg @ref LL_HRTIM_RESETTRIG_MASTER_CMP4
+ * @arg @ref LL_HRTIM_RESETTRIG_EEV_1
+ * @arg @ref LL_HRTIM_RESETTRIG_EEV_2
+ * @arg @ref LL_HRTIM_RESETTRIG_EEV_3
+ * @arg @ref LL_HRTIM_RESETTRIG_EEV_4
+ * @arg @ref LL_HRTIM_RESETTRIG_EEV_5
+ * @arg @ref LL_HRTIM_RESETTRIG_EEV_6
+ * @arg @ref LL_HRTIM_RESETTRIG_EEV_7
+ * @arg @ref LL_HRTIM_RESETTRIG_EEV_8
+ * @arg @ref LL_HRTIM_RESETTRIG_EEV_9
+ * @arg @ref LL_HRTIM_RESETTRIG_EEV_10
+ * @arg @ref LL_HRTIM_RESETTRIG_OTHER1_CMP1
+ * @arg @ref LL_HRTIM_RESETTRIG_OTHER1_CMP2
+ * @arg @ref LL_HRTIM_RESETTRIG_OTHER1_CMP4
+ * @arg @ref LL_HRTIM_RESETTRIG_OTHER2_CMP1
+ * @arg @ref LL_HRTIM_RESETTRIG_OTHER2_CMP2
+ * @arg @ref LL_HRTIM_RESETTRIG_OTHER2_CMP4
+ * @arg @ref LL_HRTIM_RESETTRIG_OTHER3_CMP1
+ * @arg @ref LL_HRTIM_RESETTRIG_OTHER3_CMP2
+ * @arg @ref LL_HRTIM_RESETTRIG_OTHER3_CMP4
+ * @arg @ref LL_HRTIM_RESETTRIG_OTHER4_CMP1
+ * @arg @ref LL_HRTIM_RESETTRIG_OTHER4_CMP2
+ * @arg @ref LL_HRTIM_RESETTRIG_OTHER4_CMP4
+ * @arg @ref LL_HRTIM_RESETTRIG_OTHER5_CMP1
+ * @arg @ref LL_HRTIM_RESETTRIG_OTHER5_CMP2
+ */
+void hrtim_rst_evt_en(hrtim_t dev, hrtim_tu_t tu, uint32_t evt);
+
+/**
+ * @brief Disbable a TimerX (X = A,B...F) reset event
+ *
+ * @param[in] dev HRTIM device
+ * @param[in] tu Timing unit, can be one of the following values:
+ * @arg @ref TIMA
+ * @arg @ref TIMB
+ * @arg @ref TIMC
+ * @arg @ref TIMD
+ * @arg @ref TIME
+ * @arg @ref TIMF
+ * @param[in] evt Reset event, can be one of the following values:
+ * @arg @ref LL_HRTIM_RESETTRIG_NONE
+ * @arg @ref LL_HRTIM_RESETTRIG_UPDATE
+ * @arg @ref LL_HRTIM_RESETTRIG_CMP2
+ * @arg @ref LL_HRTIM_RESETTRIG_CMP4
+ * @arg @ref LL_HRTIM_RESETTRIG_MASTER_PER
+ * @arg @ref LL_HRTIM_RESETTRIG_MASTER_CMP1
+ * @arg @ref LL_HRTIM_RESETTRIG_MASTER_CMP2
+ * @arg @ref LL_HRTIM_RESETTRIG_MASTER_CMP3
+ * @arg @ref LL_HRTIM_RESETTRIG_MASTER_CMP4
+ * @arg @ref LL_HRTIM_RESETTRIG_EEV_1
+ * @arg @ref LL_HRTIM_RESETTRIG_EEV_2
+ * @arg @ref LL_HRTIM_RESETTRIG_EEV_3
+ * @arg @ref LL_HRTIM_RESETTRIG_EEV_4
+ * @arg @ref LL_HRTIM_RESETTRIG_EEV_5
+ * @arg @ref LL_HRTIM_RESETTRIG_EEV_6
+ * @arg @ref LL_HRTIM_RESETTRIG_EEV_7
+ * @arg @ref LL_HRTIM_RESETTRIG_EEV_8
+ * @arg @ref LL_HRTIM_RESETTRIG_EEV_9
+ * @arg @ref LL_HRTIM_RESETTRIG_EEV_10
+ * @arg @ref LL_HRTIM_RESETTRIG_OTHER1_CMP1
+ * @arg @ref LL_HRTIM_RESETTRIG_OTHER1_CMP2
+ * @arg @ref LL_HRTIM_RESETTRIG_OTHER1_CMP4
+ * @arg @ref LL_HRTIM_RESETTRIG_OTHER2_CMP1
+ * @arg @ref LL_HRTIM_RESETTRIG_OTHER2_CMP2
+ * @arg @ref LL_HRTIM_RESETTRIG_OTHER2_CMP4
+ * @arg @ref LL_HRTIM_RESETTRIG_OTHER3_CMP1
+ * @arg @ref LL_HRTIM_RESETTRIG_OTHER3_CMP2
+ * @arg @ref LL_HRTIM_RESETTRIG_OTHER3_CMP4
+ * @arg @ref LL_HRTIM_RESETTRIG_OTHER4_CMP1
+ * @arg @ref LL_HRTIM_RESETTRIG_OTHER4_CMP2
+ * @arg @ref LL_HRTIM_RESETTRIG_OTHER4_CMP4
+ * @arg @ref LL_HRTIM_RESETTRIG_OTHER5_CMP1
+ * @arg @ref LL_HRTIM_RESETTRIG_OTHER5_CMP2
+ */
+void hrtim_rst_evt_dis(hrtim_t dev, hrtim_tu_t tu, uint32_t evt);
/**
* @brief Enable a given output of a given timing unit.
*
- * @param[in] dev HRTIM device
- * @param[in] tu Timing unit
- * @param[in] out Output to enable
+ * @param[in] dev HRTIM device
+ * @param[in] tu Timing unit, can be one of the following values:
+ * @arg @ref TIMA
+ * @arg @ref TIMB
+ * @arg @ref TIMC
+ * @arg @ref TIMD
+ * @arg @ref TIME
+ * @arg @ref TIMF
+ * @param[in] out Output to enable, can be one of the following values:
+ * @arg @ref OUT1
+ * @arg @ref OUT2
*/
void hrtim_out_en(hrtim_t dev, hrtim_tu_t tu, hrtim_out_t out);
/**
* @brief Disable a given output of a given timing unit.
*
- * @param[in] dev HRTIM device
- * @param[in] tu Timing unit
- * @param[in] out Output to disable
+ * @param[in] dev HRTIM device
+ * @param[in] tu Timing unit, can be one of the following values:
+ * @arg @ref TIMA
+ * @arg @ref TIMB
+ * @arg @ref TIMC
+ * @arg @ref TIMD
+ * @arg @ref TIME
+ * @arg @ref TIMF
+ * @param[in] out Output to disable, can be one of the following values:
+ * @arg @ref OUT1
+ * @arg @ref OUT2
*/
void hrtim_out_dis(hrtim_t dev, hrtim_tu_t tu, hrtim_out_t out);
@@ -517,9 +751,15 @@ void hrtim_out_dis(hrtim_t dev, hrtim_tu_t tu, hrtim_out_t out);
* @brief Setup a dead time in nano second for given complementary
* outputs.
*
- * @param[in] dev HRTIM device
- * @param[in] tu Timing unit
- * @param[in] ns The desired dead time in nano second
+ * @param[in] dev HRTIM device
+ * @param[in] tu Timing unit, can be one of the following values:
+ * @arg @ref TIMA
+ * @arg @ref TIMB
+ * @arg @ref TIMC
+ * @arg @ref TIMD
+ * @arg @ref TIME
+ * @arg @ref TIMF
+ * @param[in] ns The desired dead time in nano second
*/
void hrtim_pwm_dt(hrtim_t dev, hrtim_tu_t tu, uint16_t ns);
@@ -528,8 +768,8 @@ void hrtim_pwm_dt(hrtim_t dev, hrtim_tu_t tu, uint16_t ns);
* how many potential events will be ignored between two
* events which are effectively generated.
*
- * @param[in] dev HRTIM device
- * @param[in] ps_ratio Post scaler ratio (0 = no post scaler, default)
+ * @param[in] dev HRTIM device
+ * @param[in] ps_ratio Post scaler ratio (0 = no post scaler, default)
*/
void hrtim_adc_trigger_set_postscaler(hrtim_t dev, uint32_t ps_ratio);
@@ -538,7 +778,78 @@ void hrtim_adc_trigger_set_postscaler(hrtim_t dev, uint32_t ps_ratio);
*
* @param[in] event_number Number of the event to configure
* @param[in] source_timer Source timer of the event. 0 = Master timer, 1 = Timer A, 2 = Timer B, etc.
- * @param[in] event Event as defined in stm32g4xx_ll_hrtim.h 'ADC TRIGGER X/X SOURCE'
+ * @param[in] event Trigger event
+ * For ADC trigger 1 and ADC trigger 3 this parameter can be a
+ * combination of the following values:
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_NONE
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP1
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP2
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP3
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP4
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MPER
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV1
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV2
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV3
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV4
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV5
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMACMP3
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMACMP4
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMAPER
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMARST
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBCMP3
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBCMP4
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBPER
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBRST
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCCMP3
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCCMP4
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCPER
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDCMP3
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDCMP4
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDPER
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMECMP3
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMECMP4
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMEPER
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMFCMP2
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMFCMP3
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMFCMP4
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMFPER
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMFRST
+ *
+ * For ADC trigger 2 and ADC trigger 4 this parameter can be a
+ * combination of the following values:
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_NONE
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP1
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP2
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP3
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP4
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MPER
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV6
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV7
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV8
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV9
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV10
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMACMP2
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMACMP4
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMAPER
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBCMP2
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBCMP4
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBPER
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCCMP2
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCCMP4
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCPER
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCRST
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDCMP2
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDCMP4
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDPER
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDRST
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP2
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP3
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP4
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMERST
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMFCMP2
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMFCMP3
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMFCMP4
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMFPER
*/
void hrtim_adc_trigger_en(uint32_t event_number, uint32_t source_timer, uint32_t event);
@@ -546,11 +857,86 @@ void hrtim_adc_trigger_en(uint32_t event_number, uint32_t source_timer, uint32_t
/**
* @brief Disbable a ADCx trigger event
*
- * @param[in] dev HRTIM device
- * @param[in] adc ADC trigger register from ADC1R to ADC4R
- * @param[in] evt Trigger event
- */
-void hrtim_adc_trigger_dis(hrtim_t dev, hrtim_adc_t adc, hrtim_adc_trigger_t evt);
+ * @param[in] dev HRTIM device
+ * @param[in] adc ADC trigger register, can be one of the following values:
+ * @arg @ref ADC1R
+ * @arg @ref ADC2R
+ * @arg @ref ADC3R
+ * @arg @ref ADC4R
+ * @param[in] evt Trigger event
+ * For ADC trigger 1 and ADC trigger 3 this parameter can be a
+ * combination of the following values:
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_NONE
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP1
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP2
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP3
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP4
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MPER
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV1
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV2
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV3
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV4
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV5
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMACMP3
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMACMP4
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMAPER
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMARST
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBCMP3
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBCMP4
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBPER
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBRST
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCCMP3
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCCMP4
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCPER
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDCMP3
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDCMP4
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDPER
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMECMP3
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMECMP4
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMEPER
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMFCMP2
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMFCMP3
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMFCMP4
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMFPER
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMFRST
+ *
+ * For ADC trigger 2 and ADC trigger 4 this parameter can be a
+ * combination of the following values:
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_NONE
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP1
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP2
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP3
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP4
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MPER
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV6
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV7
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV8
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV9
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV10
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMACMP2
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMACMP4
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMAPER
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBCMP2
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBCMP4
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBPER
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCCMP2
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCCMP4
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCPER
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCRST
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDCMP2
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDCMP4
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDPER
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDRST
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP2
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP3
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP4
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMERST
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMFCMP2
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMFCMP3
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMFCMP4
+ * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMFPER
+ */
+void hrtim_adc_trigger_dis(hrtim_t hrtim, hrtim_adc_t adc, uint32_t evt);
diff --git a/zephyr/modules/owntech_hrtim_driver/zephyr/src/voltage_mode/owntech_leg_driver.cpp b/zephyr/modules/owntech_hrtim_driver/zephyr/src/voltage_mode/owntech_leg_driver.cpp
index 0650a00..f646e11 100644
--- a/zephyr/modules/owntech_hrtim_driver/zephyr/src/voltage_mode/owntech_leg_driver.cpp
+++ b/zephyr/modules/owntech_hrtim_driver/zephyr/src/voltage_mode/owntech_leg_driver.cpp
@@ -25,6 +25,7 @@
* @author Hugues Larrive <hugues.larrive@laas.fr>
* @author Antoine Boche <antoine.boche@laas.fr>
* @author Luiz Villa <luiz.villa@laas.fr>
+ * @author Ayoub Farah Hassan <ayoub.farah-hassan@laas.fr>
*/
#include "leg.h"
@@ -36,6 +37,34 @@ static uint16_t period, min_pw, max_pw, dead_time;
static leg_conf_t leg_conf[6]; /* a copy of leg_config with index
* corresponding to timing unit */
+static uint8_t _TU_num(hrtim_tu_t tu){
+
+ switch(tu){
+ case TIMA:
+ return 0;
+
+ case TIMB:
+ return 1;
+
+ case TIMC:
+ return 2;
+
+ case TIMD:
+ return 3;
+ break;
+
+ case TIME:
+ return 4;
+
+ case TIMF:
+ return 5;
+
+ default:
+ return 100;
+
+ }
+}
+
/**
* This function Initialize the hrtim and all the legs
* with the chosen convention for the switch controlled
@@ -49,7 +78,7 @@ uint16_t leg_init(bool leg1_upper_switch_convention, bool leg2_upper_switch_conv
/* ensures that timing_unit can be used as leg identifier */
for (unsigned int i = 0; i < LEG_NUMOF; i++)
{
- leg_conf[leg_config[i].timing_unit] = leg_config[i];
+ leg_conf[_TU_num(leg_config[i].timing_unit)] = leg_config[i];
}
period = hrtim_init(0, &freq, LEG_DEFAULT_DT,leg1_upper_switch_convention,leg2_upper_switch_convention);
@@ -59,6 +88,30 @@ uint16_t leg_init(bool leg1_upper_switch_convention, bool leg2_upper_switch_conv
return period;
}
+/**
+ * This function Initialize the hrtim and all the legs
+ * with the chosen convention for the switch controlled
+ * on the power converter to a frequency of 200kHz
+ * with the counter on up-down mode (center-alligned)
+ * Must be initialized in first position
+ */
+uint16_t leg_init_center_aligned(bool leg1_upper_switch_convention, bool leg2_upper_switch_convention)
+{
+ uint32_t freq = LEG_FREQ;
+
+ /* ensures that timing_unit can be used as leg identifier */
+ for (unsigned int i = 0; i < LEG_NUMOF; i++)
+ {
+ leg_conf[_TU_num(leg_config[i].timing_unit)] = leg_config[i];
+ }
+
+ period = hrtim_init_updwn(0, &freq, LEG_DEFAULT_DT,leg1_upper_switch_convention,leg2_upper_switch_convention);
+ dead_time = (period*LEG_DEFAULT_DT*leg_get_freq())/1000000;
+ min_pw = (period * 0.1) + dead_time;
+ max_pw = (period * 0.9) + dead_time;
+ return period;
+}
+
void leg_set(hrtim_tu_t timing_unit, uint16_t pulse_width, uint16_t phase_shift)
{
//addition of the dead time for the rectification of the centered dead time configuration cf:hrtim_pwm_dt()
@@ -74,24 +127,24 @@ void leg_set(hrtim_tu_t timing_unit, uint16_t pulse_width, uint16_t phase_shift)
pulse_width = max_pw;
}
- hrtim_pwm_set( leg_conf[timing_unit].hrtim,
+ hrtim_pwm_set( leg_conf[_TU_num(timing_unit)].hrtim,
timing_unit,
pulse_width,
phase_shift);
/* save the pulse_width */
- leg_conf[timing_unit].pulse_width = pulse_width;
+ leg_conf[_TU_num(timing_unit)].pulse_width = pulse_width;
}
void leg_stop(hrtim_tu_t timing_unit)
{
- hrtim_out_dis(leg_conf[timing_unit].hrtim, leg_conf[timing_unit].timing_unit, OUT1);
- hrtim_out_dis(leg_conf[timing_unit].hrtim, leg_conf[timing_unit].timing_unit, OUT2);
+ hrtim_out_dis(leg_conf[_TU_num(timing_unit)].hrtim, leg_conf[_TU_num(timing_unit)].timing_unit, OUT1);
+ hrtim_out_dis(leg_conf[_TU_num(timing_unit)].hrtim, leg_conf[_TU_num(timing_unit)].timing_unit, OUT2);
}
void leg_start(hrtim_tu_t timing_unit)
{
- hrtim_out_en(leg_conf[timing_unit].hrtim, leg_conf[timing_unit].timing_unit, OUT1);
- hrtim_out_en(leg_conf[timing_unit].hrtim, leg_conf[timing_unit].timing_unit, OUT2);
+ hrtim_out_en(leg_conf[_TU_num(timing_unit)].hrtim, leg_conf[_TU_num(timing_unit)].timing_unit, OUT1);
+ hrtim_out_en(leg_conf[_TU_num(timing_unit)].hrtim, leg_conf[_TU_num(timing_unit)].timing_unit, OUT2);
}
uint16_t leg_period(void)
--
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