Commit 7cb37a3c authored by Andy XU's avatar Andy XU
Browse files

added details

parent afbd717b
......@@ -38,7 +38,7 @@ Pour générer le Verilog correspondant, le format de la commande du terminal es
sbt "runMain <nom-librairie>.<nom-design> --target-dir <destination>"
```
*--target-dir* esy une option permettant de choisir le répertoire où sera généré le module Verilog correspondant.
*--target-dir* est une option permettant de choisir le répertoire où sera généré le module Verilog correspondant.
Dans l'exemple Adder, il est possible de générer le module Verilog avec la commande suivante:
```
......@@ -95,6 +95,7 @@ On retrouve ensuite dans le terminal le résultat des différents tests.
- [Informations](https://github.com/freechipsproject/chisel3)
- [Livre tutoriel](https://github.com/schoeberl/chisel-book) [(pdf)](http://www.imm.dtu.dk/~masca/chisel-book.pdf)
- [Bootcamp](https://mybinder.org/v2/gh/freechipsproject/chisel-bootcamp/master)
- [Tutoriel](https://github.com/ucb-bar/chisel-tutorial)
- VPU et RISC-V:
- [Spécification RISC-V](docs/riscv-spec.pdf)
- [Spécification RISC-V "V" Vector](docs/riscv-v-spec-1.0.pdf)
......
......@@ -24,7 +24,9 @@
- [x] _@0xC21_ vtype: vector data type register _[lmul(3bits), sew(3bits), vta(1bit), vma(1bit)]_
- [x] _@0xC22_ vlenb: vector length in byte _(VLEN/8=16)_
- Register controler (RegFile): addresses vector registers
- Register controler (Register File): addresses vector registers
- ALU, MUL, FPU
- Memory banks
---
......@@ -41,50 +43,63 @@
2. Check used vl and vtype _(sew, lmul)_
3. Feed operands with correct EEW to ALU
4. Compute #VL EEW elements
> for(#VL): vd[i] = v1[i] + v2[i]
> for(#VL): vd[i] = v1[i] + v2[i]
5. Return result in vd
### LOAD
1. Decode instruction: @vd, width, @rs1 _{@rs2(stride)/@vs2(offset)}_
2. Check used vl
3. Retrieve #VL width sized elements at @rs1 in memory {every #r2 byte}
> for(#VL): vd[i] = mem[@rs1 + i {+r2}]
> for(#VL): vd[i] = mem[@rs1 + i {+r2}]
4. Return result in vd
### STORE
1. Decode instruction: @vs3, width, @rs1 _{@rs2(stride)/@vs2(offset)}_
2. Check used vl
3. Store #VL width sized elements from vs3 to @rs1 in memory
> for(#VL): mem[@rs1 + i {+r2}] = v3[i]
> for(#VL): mem[@rs1 + i {+r2}] = v3[i]
---
## Questions
- **Control unit**
Need for instructions gathering unit for further redirection
### Control unit
- Need for instructions gathering unit for further redirection
- How to propagate instruction
- **Number of fonctionnal unit**
Simultaneous execution of multiple elements (SIMD) to improve performance
How to feed the correct element for each unit at each time
### Functional unit
- Simultaneous execution of multiple elements (SIMD) to improve performance
- How to feed the correct element for each unit at each time
- Different units for different EEW (8bits to 64bits)
- **Pipeline**
Increase performance with chaining
Sequencer for instruction parallelism and data conflict
### Memory banks
- Multiple memories/ports to increase simultaneous/parallel throughput for LOAD/STORE
- How to feed multiple data with correct size
- **VL**
How to process n element in vector register
> loop #VL times for each address of each element
### Pipeline
- Caches
- Instruction buffers
- Increase performance with chaining
- Instruction parallelism and data dependencies/conflicts
- **EEW**
How to modulate size of an element in vector register
> consider each vector register as 16\*8bits registers
### VL
- How to process n element in vector register
> loop #VL times for each address of each element
How to address one element at a time
### EEW
- How to modulate size of an element in vector register
> consider each vector register as 16\*8bits registers
- How to address one element at a time
> address one element by grouping each byte according to need
- **BUS (64bits)**
Number of buses: number of data bus for parallel execution
> at least one data bus for each functional unit
How to map registers with modular size elements to units (8-64bits)
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### BUS (64bits)
- Number of buses
> at least one data bus for each element for each functional unit
- Single data bus with buffers
- multi data bus for parallel execution
- How to map registers with modular size elements to units (8-64bits)
- Link with BASE general purpose registers
### Register File
- Register renaming
- Single or multi port
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