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Linux Module for : 1) R/W mmio registers. 2) Context change send info. 3) Interrupts handler.

Bootloader (@6000_0000) that receive file from UART and write to DDR (@8000_0000)

Build benchmark for RISC-V (default to RV64IMAC)

This is the official Low Side Synchronous Buck converter Gitlab

Quick start library for OwnTech Power API.

A generator of Return-Oriented Programming on RISC-V

arduino software hat for arduino-lmic

The Core project is the main repository intended to be cloned by end-users.

It provides all the configuration required to begin a project with OwnTech Power API, and includes the ability to automatically download OwnTech libraries.

Cache side channel attacks for RISC-V (also works for x86)

The PID library for OwnTech Power API provides boost and buck PID for voltage mode.

CMake-ified version of PythonQt

OpenSceneGraph git repository

Try to adapt Mastik Toolkit to RISC-V

Learning value function and warmstart policies.

Modification of RISC-V softcore processor Orca.

REHAD: Using Low-Frequency Reconfigurable Hardware for Cache Side-Channel Attacks Detection. Run on ML605 evaluation board with UART 115200.

Generate ROM with attacks for Rehad-Orca.

For synthesis, place mem.hex in ip/idram/src/input. [Request GCC cross compiler (RV32IM).] For bitsteam, replace BRAM content of myorca.bit. [Request Xilinx ISE setup and liscence.]